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30 Threads found on edaboard.com: Sdram Interfacing
Hi, I have a Nios system with Qsys components such as Interval timer, UART, sdram and some PIOs. My system specifications are DE0 Nano, Quartus 12.1 sp1, Altera monitor program. Nios II system are interfacing with several VHDL blocks. I am able to read data from FPGA to Nios processor, then transmit this data to Uart component
Hello, i'm working with LPC1788 and i have working LPC1788 development board, in that development board 2 sdram use for LCD data One sdram for D0 to D15 and other for D16 to D31, all control lines and adress lines are common for both sdram. this board work fine. sdram use: 4M X 16 bit X 4 banks Part No: MT48LC16M16A2 , (...)
Hi everyBody, I implement an xps system by using the Bus PLB. My IP core is added to the system using Create or Import Peripheral... I want to know how can Microblaze write several data to DDR2 sdram and how the IP core read all the data from this memory, modify it and write it back to DDR2 sdram via the PLB Bus interface. Therefore, I woul
can anyone suggest an example design for microblaze to ext memory interfacing using a controller ?? im using virtex6 fpga on ml605 .. i face some problem with connecting the ddr3 to mb ...kindly help me on this
hi dear i want to interface Micron's sdram MT48LC4M32B2 with the spartan-6 and want to use the built in memory controller. i am confused about how should DQM0-DQM3 pins be connected to DDR or DDR2 there are LDQS, UDQS nd LDM,UDM pins. can i avail this MCB feature of spartan-6 moreover this sdram is being powered by 3.3V ?? can i
hi I have implemented the code for interfacing DDR3 sdram to an FPGA but finding few errors when is id getting translate. How can i overcome with the following errors; ERROR:NgdBuild:604 - logical block 'INST_Buttons_VHDL' with type 'Buttons_VHDL' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismat
Hi i got code for DDR3 but getting some errors please can any1 check this and suggest me what to to do...... `timescale 1ps / 1ps module ddr3_model ( ck, ck_n, cke, cs_n, ras_n, cas_n, we_n, dm_rdqs, ba, addr, dq, dqs, dqs_n, rdqs_n, odt ); `include "ddr3_m
first question -- what is "an". both xilinx and altera have different solutions for different FPGAs. sdram has a protocol, and the controlller tries to handle the protocol while presenting the user with a simple interface. You typically need to research the specific FPGA options, as there may be IO requirements that are important. for example,
I would start from here: . MIG is available in Xilinx Core Generator tool, which generates Verilog or VHDL code for DDR3 memory controller. Hi Can any1 plzz help me writing a vhdl/verilog code for interfacing DDR3 sdram to vertex6 FPGA or spartran6 FPGA.... Thank
Does anyone know how to interface a DDR2 sdram on an Altera Stratix III DSP Development Kit using Quartus II 11.0?
Hi all, I am interfacing DDR2 sdram Controller in FPGA and I don't understand how can to read and write data to memory device using Microblaze processor and DDR2 sdram controller?. I'm studying about this controller and I don't know the operation of DQS signal in transferring data and the mechanism of delay DQS. who can help me? Thanks (...)
dear all i am using ise 12.1 (ip core-> memory interfacing generator) i read about this tools and i know that it is {tool generates DDR sdram interfaces Spartan-3E. The tool takes inputs such as the memory interface type, FPGA family, FPGA devices, frequencies, data width, memory mode register values, and so forth, from the user through a grap
hi guys, i want to interface sdram IS42S16160B with vertix 5 FPGA. we want to write data on sdram and then read it back, but we are facing some problem. Here is a part of code which we have written. we need some help. Regards Talha INIT: begin #(33000*full
I'm interfacing a FPGA memory controller point to point to a 512Mb DDR2 sdram. What type of termination is needed on the address/DQ/we/cas/etc signals? The chip can clock up to 400mhz (800mhz ddr)
If I understand correctly that testbench is made by Micron for the purpose of verification, right? As in not for the purpose of synthesis. If so, then I would not be surprised if it doesn't do what you want when synthesized. To interface the spartan3 to sdram you need some sdram controller IP from xilinx, or from places like [url=opencore
Hi Recently i get sample of freescale IMX27 ARM9 processors. I want to build working evaluation board,but i am stuck to availability of low power,low voltage sdram to interface with IMX27.When i open my old Pentium III mainboard,i found a 168 pin sdram module, size is 128 MB,and the sdram IC used is HY57V28820HC, 4 Banks x 4M x 8bits (...)
I am interfacing an DDR2 sdram with my application.I want to know the maximum trace length for routing of Address and control signals based on the Frequency of my sdram Please let me know how to calculate ,formulas for calculating the trace length Regards Rajan.k
I am doing a project where in i need to interface ddr sdram . In order to do that i tried to study ddr sdram datasheet but failed to comprehend it . Itused to talk about signals as if the signals as if the reader is already aware of them . can you please suggest a good resource that could help me in understanding the ddr sdram esp. from (...)
Hi, I am trying to Interface DDR sdram with Spartan3. I am using MIG_V2.3 to generate Interface block. When I am doing PAR, I am getting the following error..... ----------------------------------------------------------------------------------------------- Resolving constraint associations... Checking Constraint Associations... ERROR:C
Hi, Factors needs to be consider when interfacing DSP with sdram. Step need to be checked while selecting a sdram. Thanks, Jamesh