Search Engine www.edaboard.com

Seperate Vdd

Add Question

5 Threads found on edaboard.com: Seperate Vdd
Hello In few standard cells, bulk of PMOS and NMOS are usually given a seperate bulk Voltages ,unlike the normal shorting of bulk to vdd and VSS in PMOS and NMOS respectively. Why is it done so? And would the Bulk voltages be higher or lesser than the supply voltages? Please share any docs related to the same concept. Thanks BB
on the top level layout, analog power rail should be abut each other and so is that for digital power rail. So for different voltage domain, that is, u dont wanna connect the analog power1 to analog power2 by abuting together, then u can use power cut cell to make it seperated. arsenal
Hey even if there is externally only one pin, you can generate a seperate vdd with an internal regulator. In most of the Power Management SoCs, you have an internal regulator to power up the digital. Remember these things can save a lot of real-estate on the board and hence is more cost effective.
Hi, i have a question on the substrate connection for mixed signal circuit with p-sub lightly-dopled submicron cmos process. In my mixed block, we have seperate analog vdd/gnd and digital vdd/gnd for crosstalk reduction from digital part. I want to know the substrate connection, in my cicruit, i connected it to the analog gnd for which (...)
SOME VENDORS IMPLEMENT 0 OHM RESISTOR OR FERRITE BEADS TO seperate PLL DIGITAL/ANALOG GND AND VOLTAGE. THE IDEA BEYOND THE DIRECT CONNECTION IS ELECTRICALLY SIMILAR TO THE 0 OHM APPROACH BUT GIVE YOU MORE BENEFITS LIKE LESS DS ATTENUATION, AND ABILITY TO PASS SIGNALS ABOVE AND BELOW THIS CONNECTION AND NOT THROUGHT PLANE SPLIT. THE DISSAD