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82 Threads found on edaboard.com: Sequential And Combinational
137319 Hi, It is a ISRO question in 2015. Can somebody give a clear understanding of FPGA resources and where actually the board keeps the combo logic and sequential logic after programmed.
Can anyone tell me,how to determine the number of faults detected per test vector? How to write verilog code for that?Please suggest me
Perhaps the hardship you're facing is due to the lack of the skills in electronics. For those who have already some background in combinational and sequential logic, the HDL comes intuitive. You have to remind that VHDL should not be considered as a programming language, but rather a descriptive language. I would recommend you search for (...)
In terms of design logic, i heard somewhere that any logic without a feedback path (i.e combinational) fits into the LUTS. and sequential logic or control path design sits inside flipflops. am i correct, please correct me
I was working on my project with logic, sequential and combinational ICs. and, wanted to test the 74LS10 3-input Nand gate and it wasn't working!! All other ICs are working, NOR, 2-input Nand, counter, 555 timer. I've other 74LS10, if they all not working then I'd (...)
You may like to check existing SPI code ( in verilog or VHDL as the case may be) and see how you can use it to interface with the RF nodule. SPI interface comes under sequential circuits and a combinational only device will not work.
Hi I have designed a sequential cell that computes a logic function. I want to use this cell as combinational cell because both its clock and data are generated independently (there is no global clock). Therefore I am using data-to-data setup check in RTL compiler. I am able to let the tool know that such checks should be performed (...)
In general I would expect DRC and Monte Carlo methods will determine critical timing and path length issues. Critical path (shortest latency) results should come out of a manual or auto generated set of test vectors in combinational and sequential table and generate the results which could (...)
You need to learn the difference between blocking (=) and non-blocking (<=) assignments. You should search either this forum or use google. in summary = for combinational logic, <= for sequential logic (i.e. flip-flops). Also you should use a synchronously deasserted reset, there is an
You're performing an and operation with a clock and a bus? if (clk & h_end)what do you expect this bitwise and to evaluate to? Using the clock in this fashion is not a good design practice in FPGAs. You are also using non-blocking statements in a combinational always block: always @(*) if(clk & h_end) if(v_count
i request you to let me know if the following is correct 1. the power consumed in circuit is sum of the power consumed in its components. if a circuit has sequential and combinational components, then power of the sequential component = power of whole circuit - power of combinational component. Thank (...)
You are assigning values to i in multiple procedural blocks, which isn't allowed. See. @(posedge PWM_o) and @(posedge count) blocks. You are using the multi-bit output reg count as a clock, this won't synthesized correctly (should probably result in an error, but I've never tried this). Then you also use the count value in th
Hi, I am using Design Compiler to synthesize a sequential design. I want to find all the cells (including combinational and sequential) from a given input to an output. I know that I can use "all_fanin". But the problem is that it stops at the clock of the sequential elements. I am wondering if there is a (...)
I have read CMOS DIgital Integrated Circuits by Kang, Leblebici. I need some advanced level book on Digital VLSI Design. The book should cover combinational & sequential designs in details. No need for MOS device physics, interconnet and device capacitances, etc. Can anyone suggest me some good books?
Without register or flop , you can not perform shift operation. Give more detail on this , like block diagram .. A shift operation can be well performed in combinational expressions and won't use registers respectively. Clock synchronous sequential shifts using registers are possible, too. The question is about the specificatio
You'll analyze thoroughly where the design resources go. In some cases, parallel can be replaced by sequential logic.
I've seen RTL implementations where 1. Only sequential always block is used, always@(posedge clk), with assign statements for combinational logic 2. Comb and sequential always block is used, always@(*) and always@(posedge clk) to separate the comb and seq logic I have two questions: (...)
Question: Make Calendar Which Shows Month Number and Days of Month ? Write Both in combinational and sequential VHDL Constructs ? I am new on this VHDL and i have a quiz on Monday .. Anyone have any idea about where to start and how to start writing the programming in VHDL ? Any help (...)
hai members i need to test combinational and sequential circuits by applying test vectors,i checked for it only verilog files are available for those circuits,iam using tanner and microwind .give me your suggestions
hi to all, i generated test patterns and tested the small input c17 combinational benchmark circuit using basic D algorithm. i feel trouble when go for higher circuits and the method is not feasible to test large input bench mark circuits practically. how to do the testing of combinational circuits practically ?.