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30 Threads found on Serdes Design
Dear Friends, I am new to hardware design. I am designing a burst mode CDR. I have 8 phase input clock. I am sampling the input data with this clock. I am preparing an algorithm for detecting the phase which sample the data at mid point. Typically my clock should lock to the incoming data in no time. There are scripts available which describes
Dear Friends, I am newbie to hardware design. I have a task to design a burst mode CDR. Typically it should have very fast frequency acquisition time. In my system, I have a 8 phase clock input. I am sampling my data with this clock. Now I am searching for an algorithm to detect the phase at the mid point of the data (thereby locks in no time). I
PIPE (Physical Interface for PCIe), is a set of analog PHY standards developed by Intel to control the analog circuitry (PMA inside the PHY where serdes and PLL reside) design within certain requirements. It's essentially guidelines put in place for IP developers to ensure widespread compliance among vendors. PCISIG is a goo
Hi guys...... I am new to analog layout design. I want to prepare my resume.I want these modules on layout 1. serdes. 2.PLL. 3.ADC. 4.Standard Cells 5.BGR. Can anybody kindly Please send me the model resume on the above mentioned topics regarding layout.:-D My email id : Thanks & Regards Ravi te
Hello all! I'm (desperately) looking for reference schematic and layout example for QSFP+ interface using NLP1042 or similar quad 10GB serdes (Allegro is preferred, but any tool will do, even just the gerbers/pdf). Please contact me if you can help. I hope its a correct place to ask for such a things? Thanks!
Any circuit dealing with intermediate voltages other than high and low. Combination of above with few digital logic can also be termed as mixed signal. serdes, PLL etc.
Hi all, I am trying to model the equalizer in matlab.both Tx and Rx for PCI e 3.0 standard. it would be great if someone shares their view
i am new in designing world and this is the first main design project for me , i am responsible for the Receiving side of the high speed serial link after reading , studying many papers and putting the system of receiver by hand , i guess the next step is to make system level simulation what i need for this step ? and which software , is it
Perhaps this could give you some ideas:
Hi riyas, Can you provide me the link from where I can get to know about the information about the serdes? As I am as well working in the saem domain but want to have a detail knowledge about teh same.
i have the same question.... I'm working on serdes ... and using global foundry 28nm SLP... please help
Hi, guys, I am doing 10G serdes circuit design stuffs, I need some IEEE paper, thank you so much. (1)design and verification of multi-gigabit transmission channels using equalization techniques (2) A 6.4-Gb/s CMOS serdes core with feed-forward and decision-feedback equalization (3)Clock Recovery and Equalization (...)
could someone give me some advises or some study material about serdes, Iam a beginning of this and really feel confused now, thank you very much.
Can anyone recommend some material(books or thesis) about serdes design? Thanks.
Hi, I will be needing clock delays fpr my serdes design. At first I used inverter buffers for the clock delays on my serdes, however, these delays are vulnerable to process variation. The delays I needed are sub nanoseconds like 0.1ns. How can I possibly acquire the delay with such independence on process? Please Help :D --andrew
San Jose, CA. Pls. send your resume to serdes design effort include full understanding of 5Gb/s or higher speed of PCI-e PHY implementation which include low jitter analog PLL design with Spread Spectrum Clocking Modulation scheme, Receive equalization design technique and data/clock recovery PLL. (...)
There is an excellent career opportunity for an AMS engineer, in a company located in Heliopolis, Cairo. This company will be working exclusively with Synopsys. --Required: 1. Good understanding of serdes design. 2. Experience with 65nm or 90 nm technologies. 3. Excellent leadership skills. --Brief job description: The candidate will
I am looking at a legacy design. The design accepts 2 clocks (of same frequency and from same source), one goes to core logic and other goes to serdes block. I am not sure why an indepdent clock is fed separately to serdes while the same core clock can be used. When I refered to design document, it says (...)
Dear All, I need any references on high speed serdes design. Thanks, BR
I am interconnecting two FPGA's over LVDS where serdes modules are used on both ends. The 7:1 serdes modules are provided by Xilinx, described in the Xilinx application note xapp485. The clock is not embedded in the data but is transmitted separately with a reduced rate and reconstructed on the receiving end. I would need to implement these