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41 Threads found on edaboard.com: Setup And Hold Time Violations
Can I always set false path for violation occurring at inter-clock-path ? ( provided , CDC is taken care in RTL ) Yes. How to solve Intra-clock-path timing violations ( setup and hold ) Provided that you follow good FPGA design practices (mainly using dedicated clock routes) - hold time (...)
Hello all, I have 2 questions here setup and hold violations in same path - yes / no ? setup and hold violations on the same flop - yes / no ? I have know that setup and hold (...)
check this link Fixing setup & hold violations
Hi All, i've a confusion why worst case report is considered as the Max delay violation(setup violation) and Best case report as Min delay(hold violations). and why we always calculate the hold violations at the launching flop. thanks in advance, Arjun
The library timing defined the timing table with two axes: the output capacitance and the input transition, and also indicates max trans/cap for each pins, this value could be the limit of the axes, or smaller (not really good if this is higher than the axes). The max capacitance and max transition violations only indicate (...)
can you help me ,how to set the hold violations with out disturbing the setup path/time manually ....???
I think you should forget about primetime and study the basics of the hold time. setup time = max of all data delays - min of all clk delays. hold time = max of clock delays - min of all data delays. The clock delay will be in terms of inverters/buffer (...)
I'm a beginner at using Encounter and am running into some issues. The timing analysis reports in Encounter show no setup or hold time violations in my design. However, after I import the layout into Virtuoso and run a simulation on the PEX extracted view (R+C only), there are several (...)
Hi During preCTS the clock is considered to be am ideal clock and hence the hold violation that occurs due to skew cannot happen(as it is ideal). Hence, we go only for setup check during preCTS stage. Once CTS is done, ideal clocks are replaced by real clocks and hence skew appear which may lead to hold (...)
Primetime can do setup and hold fixing using "fix_eco_timing" command and suggest the changes. You can write the changes suggested by primetime to fix setup/hold violations using "write_changes" command. (...)
Well it depend on a lot of things like the source of clock, layout, components etc. Introducing 20% uncertainty in clock may cause setup and hold time violations in circuit.
Hello All, Is it possible that the setup violations occur in the best-case analysis (min delays) and hold violations in the worst-case analysis (max delays)? Thank you!
Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability.
STA: Is it possible to get hold-time violations during WC max-delay checks and setup-time violations during BC min delay? Please provide scenarios. Thank you!
which of the following is true regarding metastability: 1.depends on setup violation 2.depends on hold violation 3.can be seen as increase in clock to q delay 4. none of these. please tell me the ans
Hi Jeevan, Please cehck the following blog for detail... VLSI Concepts: Static Timing Analysis (STA) basic - Part3a - "setup and hold time" In short i can say that.. the setup time of a flop depends on the characteristic of the Flop. If its slow .. mean
hi all i have setup and hold met with good margin of postive slave, but i have max trans and cap violations, still i need to fix them? if so why we need to fix them even after meeting setup and hold with good margin Thanks in advance
Hi friends, Please discuss the various techniques to solve setup violations? Please elaborate on why and when we use each technique. How to take care of hold violation at the same time? Thanks in advance, Sowmya
the same path to a macro can have both a setup and hold violations. Internal to the macro there can be a short path and a long path. At high frequency with lots of margin you can get both setup and hold violations
Hi, Any timing check either setup or hold will be applicable to only Synchronous or Sequential circuit. These are not applicable to Combinatorial circuits because of its nature. -Paul