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Setup Time And Hold Time

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333 Threads found on edaboard.com: Setup Time And Hold Time
hi friends how can i design a D flip flop and calculate setup and hold time for it? Is there possible design d flip flop with PSSL family of logic ? thanks in advanced
Hi, I would like to know how does clock latency affect setup and hold time? Does it help in any way?
The question isn't silly but rather vague. Which data bus setup time are you specifically talking about? Between which bus signals?
Hello, I am about to find the setup time value for Virtex-5 FPGA (XC5VLX50T) and have looked at page 45 of the following datasheet: it provides lots of timing values except the setup time value !! I know that hold (...)
Hello all , There are times, when I am not allowed to change the RTL, and all the clocking structure in the design are already optimized. Still I face situations where I have negative slack ( setup as well as hold ) Some times by trying few strategies in Vivado, the (...)
if you have a path where two registers use the same clock enable that is a periodic clock enable, then you know that the setup and hold time can be much longer for these registers as they really only get updated once every N clocks.
A circuit an timing diagram would be needed to understand your problem. If setup and hold time violation can not be avoided(asychronous incoming signals) a synchronization with two flipflops in series could be used. The second flipflop uses a delayed clock, so that metastable states of the (...)
The set up and hold times of a FF are function of clock transition time and input transition times. What is the relation actually?? It seems the setup and hold (...)
Hi. As I know basically, in synthesis, we can get the information which is WNS,TNS, from start point to end point critical data path from synthesis schematic. Also mostly in initial synthesis, we focus/concentrate on the setup violation because the hold violation is changed from CTS flow and P&R flow. But I'm confused that the effect (...)
Hi All, I am using some memories in our design. I got the setup and hold time values of the memory from its *.lib file. But I need to test (Not only in simulation but as well as on real chip) whether the values are correct or not. Is there any way to (either standard or other) test the (...)
Hi How crosstalk impact the values of setup and hold time ?
Hi, recently I tried to simulate d-flip flop in HSPICE. I follow steps from this website ( ). I try to implement it in my netlist and it worked except for hold rise. I cant figure what's the problem, is it my code or the d-flip flop is acting weird. Here's the screenshot of the waveforms: [AT
Hi All, What's the physical explanation for the setup & hold requirements? Thank you!
Hello all, I have 2 questions here setup and hold violations in same path - yes / no ? setup and hold violations on the same flop - yes / no ? I have know that setup and hold violations cannot come on same flop as it will lead to (...)
Hello all, Suppose I am having a D flip flop. Now what are the parameters those affects the setup and hold time of the same? If I want to change it, how to change it?
check this link Fixing setup & hold Violations
Hi I saw CPPR adjustment is added in the setup path and subtracted in the hold timing. What is the Purpose of CPPR. and hold time is calculated at the same edge of clock at two flipflops... so if a hold violation occurs then there is a possibility (...)
Hi guys, I have been searching about the clock uncertainty and what I got is that it represents the maximum skew @ clock inputs of different flops for a given clock tree. If this understanding is correct kindly confirm. My question here is, what are the basis that I should use to be able to set the clock uncertainty in synthesis flow ? (...)
What is the difference between Timing analysis done in Design Compiler , Prime time and ICC Compiler. Which tool is preferred ? How do we fix setup & hold violations using Design Compiler ? Post Synthesis (library.db and gatenetlist.v are given as I/P to (...)
Hello everyone, Being a hardware design engineer, the very first time i am guiding a PCB Design Engineer on a embedded project circuit board. The Processor is interfaced with SPI lines to a Peripheral Device. On the MOSI there is a datasignal of about 10MHZ. But it appears to have the setup violations of about 20ps and (...)