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407 Threads found on edaboard.com: Setup Time Hold Time
hi friends how can i design a D flip flop and calculate setup and hold time for it? Is there possible design d flip flop with PSSL family of logic ? thanks in advanced
Hi, I would like to know how does clock latency affect setup and hold time? Does it help in any way?
The question isn't silly but rather vague. Which data bus setup time are you specifically talking about? Between which bus signals?
Hello, I am about to find the setup time value for Virtex-5 FPGA (XC5VLX50T) and have looked at page 45 of the following datasheet: it provides lots of timing values except the setup time value !! I know that hold time value is 0 (...)
setup time- it is the time before active edge of clock data must be stable otherwise it may go into the stage of metastablity(undefined state). hold time-minimum time required after the clock event to stable the data. (...)
Can I always set false path for violation occurring at inter-clock-path ? ( provided , CDC is taken care in RTL ) Yes. How to solve Intra-clock-path timing violations ( setup and hold ) Provided that you follow good FPGA design practices (mainly using dedicated clock routes) - hold time violations will rare
if you have a path where two registers use the same clock enable that is a periodic clock enable, then you know that the setup and hold time can be much longer for these registers as they really only get updated once every N clocks.
A circuit an timing diagram would be needed to understand your problem. If setup and hold time violation can not be avoided(asychronous incoming signals) a synchronization with two flipflops in series could be used. The second flipflop uses a delayed clock, so that metastable states of the first flipflop a over. Enjoy your (...)
The set up and hold times of a FF are function of clock transition time and input transition times. What is the relation actually?? It seems the setup and hold times increase with high clock transition (...)
To drive the power switch of the sim900 you need to hold on for some time. However which kind of board are you using, did you have a microcontroller as part of the setup?
Hi. As I know basically, in synthesis, we can get the information which is WNS,TNS, from start point to end point critical data path from synthesis schematic. Also mostly in initial synthesis, we focus/concentrate on the setup violation because the hold violation is changed from CTS flow and P&R flow. But I'm confused that the effect clock ske
Hi All, If ur data path is optimized ( 2 flops and a combo logic) and have setup violation,what option you use to fix setup violation ? Could u answer this ?
Hi All, I am using some memories in our design. I got the setup and hold time values of the memory from its *.lib file. But I need to test (Not only in simulation but as well as on real chip) whether the values are correct or not. Is there any way to (either standard or other) test the setup and (...)
Hi folks, I have seen few zero cycle ( set_multicycle_path 0) setup paths in design. Can you explain why there is a need of having 0 cycle setup path? what is a advantage of the same? How do we check hold violations for these kind of paths? These paths are violating setup time. How (...)
Halfcycle path helps hold or setup? and why?
Hi How crosstalk impact the values of setup and hold time ?
Hi, recently I tried to simulate d-flip flop in HSPICE. I follow steps from this website ( ). I try to implement it in my netlist and it worked except for hold rise. I cant figure what's the problem, is it my code or the d-flip flop is acting weird. Here's the screenshot of the waveforms: [AT
Hi all: I saw the following descriptions for Setting Maximum and Minimum Path Delays: pt_shell> set_max_delay 12 \ -from -to With this timing exception, Primetime ignores the clock relationships. A path delay between these registers that exceeds 12 time units minus the setup requirement of the endpoin
Hi All, What's the physical explanation for the setup & hold requirements? Thank you!
Hi, In general, right after synthesis by DC (before ECO) the number of hold violations is much greater than setup violations. Is this because DC tool puts higher priority on setup than hold optimization? Thanks, dl