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48 Threads found on edaboard.com: Sfdr Dac
Hey guys. I'm making a project to ADC flash and dac 4 bits and i have to see the sfdr to the output signal using cadence calculator. Somebody can help me? Thanks.
Hi, How to plot PSD spectrum (snr,sfdr and enob) of current steering dac output signal after simulations from Cadence? Regards, Sudeep
I have a high speed TX dac that needs to be characterized for SNR, sfdr. The output bandwidth of the dac is 1GHz. Does anyone know how to measure the above parameters with narrow band equipment?
hi, When should we care about sfdr? and when SNDR? For dac design, which should we care about? thanks, arsenal
Hi I want to calculate SNR,SNDR,sfdr,ENOB of designed ADC. I want to use matlab for processing. I have designde ADC in cadence spectra and do the tansient analysis by sine wave as the i/p. Can anyone tell me should I use ideal dac at the o/p of ADC and take the reconstructed sine signal to matlab or only digital bits of transient analysis take
Hi guys, I am simulating 3bit ΣΔ ADC using HSPICE. a 3bit-flash quantizer used in ΣΔ ADC. how can implementation ideal thermometer coded dac in hspice (using control voltage sources) to convert 7 thermometer code to one output for return the data to MATLAB, and calculating SNDR sfdr ,........... thank you very much
sfdr ~~20log(3Pi/4)+3N -20log(sigmaunit) were N is your dac resolution, and sigmaunit is the matching error standard deviation. So from a 4bit converter with a (non-)linearity of 9bit (1/512) from your FFT result you'd get sfdr ≈ 7.44 + 12 - (-54.19) ≈ 73.6 dB Is that correct? erikl
hi my friends i have been designed 10-bit 50M sample/s Successive Approximation ADC in CMOS 0.18um technology i have been used HSPICE for simulation, now i want to test my dac's sfdr, SNDR and ENOB spec in Hspice. i really have not any information about this. is there any good reference for it? i have no time for doing it, please help!!!!!!!!!!
Hello all, I have designed dac, which last stage is SC filter. The FFT analysis of SC filter output shows that sfdr is about 80dB (time interval - from A to B). Modeling is performed in Cadence design environment, strobeperiod=Fclk/10 is used, where Fclk is clocking frequency of SC Filter. When I use IDEAL LP filter after SC filter and perfo
Hi, Iam design a unit element using switches and cascade transistors now am getting the output impedance at 1GHz frequency 108dB and sfdr 65dB . Iam attaching my design How to improve output impedance in dac in 65nm design
hi folks. i am trying to test the 10 bit pipelined ADC schematic i designed. The procedure i am following for finding the SNDR is " take a sinusoidal input signal nearer to full scale range.Using an ideal dac reconstruct the signal. Plot its FFT ,say for 1024 points,take those values and find SNDR, THD, sfdr , SNR from matlab by giving those codes
Hi, Usually, for SD standards(NTSC,PAL), the video's signal bandwidth(BW) required is 4MHz. This goes upto ~30MHz for HD standards(viz., SMPTE274). The video signal is normally pre-processed in 8 bits for SD standards. Hence, the expected ENOB from the dac is 8 bits, which translates into an SNDR/SINAD
Hi, Can anyone give me some idea how I can calculate sfdr from the DFT plot obtained by using cadence ADE calculator. I want to know after getting the DFT plot, what function in the calculator do i need to choose to obtain sfdr? Thanx.
Can anybody help me
I have designed a 12 bit current streeing dac working at 2 GSPS. I have to achieve specification of sfdr 70 dBc. how to establish test setup for sfdr measurement, what i/p signal frequency I should take. what sampling frequency i should take? In one paper I read sampling frequency should not be real multiple of signal frequency so that (...)
Hi Liuguojia387, Which Process you used, 65nm or 130nm? 12b 1GSps dac with sfdr of 70dB? Though It is so popular a design, Switches and current cell may be the same as those used in 100MHz ~ 200MHz Cases. My understanding, the most tricky things to handle is high frequency Dynamics and Power Supply Spikes. Static or Low frequency Linearity maybe c
I have to measure dac for Wireless communication. When I look for the way of the how to measure dac, I found "very few people wrote down their dac's SNDR in their Paper." Most of them only measured dac's sfdr. In measuring the dac, All I have to do is to measure the (...)
Hi guys: i have designed a 12 bit current steering dac, when i calculate the sfdr of the output waveform, the verity of the value is so much. since the output wave is step by step, when i take 1 point at one step for DFT, the output sfdr is 70dB, but when i take 256 points at one step, the output sfdr is 50dB. who (...)
Hi guys: i have designed a 12 bit current steering dac, when i calculate the sfdr of the output waveform, the verity of the value is so much. since the output wave is step by step, when i take 1 point at one step, the output sfdr is 70dB, but when i take 256 points at one step, the output sfdr is 50dB. who can (...)
All of them are about the current steering dac design. 1: An accurate statistical yield model for CMOS current steering D/A converters. A.Van den Bosch, M.Steyaert and W.Sansen. 2: sfdr-bandwidth limitations for high speed high resolution current steering CMOS D/A converters . A.Van den Bosch, M.Steyaert and W.Sansen. thanks!!!!