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Sigma Delta Adc Simulation

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64 Threads found on edaboard.com: Sigma Delta Adc Simulation
Hello, I've read around extensively about FFT setup for a sigma delta adc and I'm not sure if I'm not setting it up properly . my current setup for a first order sigma delta adc sampling frequency : 38.4 kHz (for the adc and FFT setup) FFT bins : 65536 input (...)
Hi, I am designing a 3rd order, 1.5 bit (= 3 Level) quantizer Continuous Time sigma delta adc, with maximum input frequency 1 MHz, OSR = 32. The target SQNR = 75 dB. The system achieves the desired SQNR using CMOS comparator, ideal op-amp & Ideal DAC. when i tried to design the CMOS op-amp, i achieved the following specs: GBW: (...)
Okay, here's the deal: 1) Learn about coherent sampling. You should use sampling frequencies and input frequencies that are coherent. Meaning that the input frequency should always be exactly on a bin that is computed by FFT to get the most accurate performance measurement. There's more to it but this is an intuitive explanation. If you get this p
Hello I have some queries about delta-sigma DAC. 1) basically, it is same with delta-sigma adc, but it consists of digital blocks, such as accumulators. However, how to synchronize the clock with PCM signals from a DSP? Does it need serial communication circuits? 2) I tried to find Simulink (...)
Hi All, This is my first adc and verifying it is proving to be more difficult then actually designing the subblock. I have been able to do a transient simulation in cadence (spectre) and have successfully imported the data into matlab. This is where I'm encountering most of my headache. 1) I'm new at matlab 2)All of the fft examples I've
Hi, I'm working on a project about audio sigma . There are some spurious components in audio band(20Hz~20KHz) when the adc is stimulated with no signal or small amplitude signal such as 10mVpeak-to-peak 1kHz audio signal while no other analog or digital modules can generates that low frequency (such as 2.3kHz, 10kHz) components on the same chip.
have anyone done any simulation of the DSM . here is my design.. but my output seems to be inverted.. anyone know if im doing anything wrong or can explain to me why my waveform is inverted. 89268 my output bit steam when input at Vmax there should be more 1s at the top however my waveform stated otherwise. [ATTACH=CO
I am building sigma delta adc, i want to include the effect of thermal noise in the sustem.. Is there any way to include noise source to represent resistors' thermal noise ?? a random source generator or something ?
first of all u need u understand the modulator portion. it consists of 1. Loop filter which is basically an integrator in discrete time ie z tranform so u need to know about z transfroms and then how to create a filter in z-domain 2. Quantizer which is basically is 1 bit comparator which can be implemented using sign block in Matlab Simulink 3. DA
I want to model an sigma delta adc with VHDL. in this case we ned to have an LowPass RC. and for simulation also we need its model. 78976
I'm recently working on delta sigma a new on this,I started from the behavioral simulation. The topological structure is as follows: 70480 the coefficients are 0.2 0.4 0.1 0.1. However,problem is with ideal component,the PSD is stable.After replacing the ideal component with unideal component,the PSD becomes unstabl
hi... im trying to simulate sigma delta adc in cadence at behaviral lvel.... wen i used ideal integrator block in ahdl lib in cadence results came gud bt wen i try puting opamp based Integrator (used ahdl lib opamp wid Appropriate R & c values) i cudnt get the results at all...some unexpected waveforms i hope im doing some mistake in (...)
My question is that : Now that the adc is translate a analog input to a digital one, so the output of the sigma-delta adc should be a lot of digital signals, Such as 1111101111. not a sine wave.Correct. By the way, Does the software limit this simulation ?No.
when i simulate a sigma delta adc in cadence a time it is perfect another time it got bad and it is the same circuit does any one say to me why?????????????????????????????????????????????????????
sigma delta adc mat lab simulation I am trying to simulate the ∑Δ adc in simulink... on running it thr following error messages are prompted... can anybody help me how to do away with the errors.. 1) Only 'double' signals are accepted by block type Integrator. The signals at the ports (...)
I am trying to simulate the ∑Δ adc in simulink... on running it thr following error messages are prompted... can anybody help me how to do away with the errors.. 1) Only 'double' signals are accepted by block type Integrator. The signals at the ports of 'sigma_delta_adc/Integrator' are of data type 'boolean'. 2) (...)
HI GUYS i am working in mentor garphics DAIC tool for modelling the switched capacitor resonator LDI Loop for sigma delta adc. actually i want to estimate the opamp specifications for my design using a macro block present in the mentor graphics....actually my problem is while simulating i am getting some error. due to which tool do not (...)
Hi everyone I met a question in the designing the mash sigmadelta adc. In my design, it is a 2-1-1 mash, every stage has 1-bit flash. I use the scaling factor as in book(cascade sigma delta adc for sensor and telecom). I have finished the schematic, and is doing the spectre (...)
hi all, i have design a sigma delta adc. the fft results of both "matlab" and "veriloga" and "veriloga_sw & mos_amp" is fine. if the veriloga sw be changed to cmos-sw, the dc noise peak arise, & independent of fft point number. the 1/R_sw/C_s ~= 6*(2*pi*f_sample). my english is very poor, thanks for your help!! Add
Hi, all: I added dynamic dither into my adc to eliminate spurs due to offset. It is weird that the SQNR of adc with dynamic dither is higher than that without dither. Is there any one can give me an explain or tell me what could be wrong? I do the simulation in Matlab. Both are under the same configuration. Thanks