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## Sigma Delta Bit |

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multi bit delta sigma , bit width delta sigma , sigma delta second , delta sigma example

multi bit delta sigma , bit width delta sigma , sigma delta second , delta sigma example

249 Threads found on edaboard.com: **Sigma Delta Bit**

Hi Folks,
I need to design a 1 **bit** DAC for **sigma** **delta** modulator. Can anybody please suggest me some architecture for dac design?
For incremental **delta** **sigma** the dac needs to provide three state ( two states from two quantizer levels and one state for input level). How is it possible with 1 (...)

Analog Circuit Design :: 02-05-2017 03:47 :: ashrafsazid :: Replies: **1** :: Views: **918**

Hi,
I need help to determine the op amp gain required to match certain ADC specifications. I need to design a **delta** **sigma** 14 **bit** ADC and need to find out required op-amp gain for the integrator design. Is there any certain formula to find out that

Analog Circuit Design :: 10-01-2016 09:30 :: ashrafsazid :: Replies: **0** :: Views: **624**

Hello,
I?ve got problem with my 3 Stage Filter Design in MATLAB (for a **delta**-**sigma** Modulator),
it would be great if someone could help!
The **delta**-**sigma** modulator has an input signal of 1kHz and wir OSR = 512 an output of 1 MHz.
So I decided to do a 3 stage Filter: CIC w. 1 **bit** input (decimation (...)

ASIC Design Methodologies and Tools (Digital) :: 09-21-2016 13:29 :: hyperbolicus :: Replies: **0** :: Views: **1031**

Hi,
You are desgning the is a clocked system, so you should know after how much clock cycles the output is valid.
(Just to be sure: you don't talk about **delta** **sigma** ADC?)
Klaus

Analog Circuit Design :: 08-09-2016 06:26 :: KlausST :: Replies: **2** :: Views: **621**

Hi everybody,
I have a couple of questions about power spectral density simulation of the **sigma**-**delta** modulators. I want to see the harmonics inside the output **bit**-stream of the modulated signal.
The details of what I did are provided at this link:
I will be so thankful if you answer these questions:
1- How lo

Analog Circuit Design :: 12-07-2015 02:06 :: mmnavidi :: Replies: **1** :: Views: **616**

Hi Friends,
I am wondering how **sigma** **delta** ADC's work with a 1 **bit** Comparator. I went through some articles and I have a rough idea of its architecture. There's a 1 **bit** comparator and the input is sampled many more times than the Nyquist rate.
Suppose I have a 0 to 10V measuring **sigma** (...)

Analog Circuit Design :: 10-07-2015 06:05 :: pawan kumar :: Replies: **6** :: Views: **1242**

hello all
I have two queries on **sigma** **delta** ADC
1. While going through its material i found that while some show that the output of the modulator is series of 0s and 1s, some show it as series of 1 and -1.
Which is correct
2. The output of decimator is shown as a discrete signal and not a digital (0 and 1). but the ADC should give a

Analog Circuit Design :: 10-19-2015 08:15 :: sona_ :: Replies: **20** :: Views: **2954**

A strange phenomenon appears when I was testing my **sigma** **delta** ADC(MASH 2-1 structure, with single **bit** quantizer at both stages) . The small signal (10mVpeak-peak, 2.9Vpeak-peak as FS value) 1kHz sine wave is used as stimulus to the data converter and 2nd, 3rd, 4th, 5th harmonic distortions can be observed in Audio Precision measurement's (...)

Analog Circuit Design :: 05-18-2015 06:26 :: threekingtiger :: Replies: **3** :: Views: **747**

Hi,
We are trying to interface Shunt 75mV at 500 Amps AD/DC load to PIC24FJ128GC006 microcontroller,
Can we connect shunt directly to Micro controller CH0+ and CH0- pins or do we need any circuit in between. PIC24FJxxxGCyyy series micro controllers have inbuilt 16 **bit** **sigma** **delta** ADC. So considering the resolution we think that 0.1 (...)

Microcontrollers :: 05-16-2015 09:47 :: gravi :: Replies: **25** :: Views: **2813**

I need some help understanding **delta** **sigma** data converters.
Suppose I have a 16 **bit** **delta** **sigma** ADC, a sampling clock at 100kHz and an oversampling ratio of 64. I want to calculate samples per second.
A 16 **bit** converter requires 2^N clocks; 65536 clocks in this case. If my sampling (...)

Elementary Electronic Questions :: 02-24-2015 20:56 :: L.A.W. :: Replies: **3** :: Views: **915**

To achieve 16 **bit** resolution with 44 kHz sampling rate using regular PWM, you would need about 3 GHz pwm clock. That's obviously not feasible.
Some kind of **sigma**-**delta** modulation is necessary.

Microcontrollers :: 02-13-2015 22:34 :: FvM :: Replies: **8** :: Views: **1724**

Hi.....
I have designed and fabricated a 16**bit** second order, single **bit** **sigma** **delta** modulator based ADC. During testing of ADC, when we apply zero volt at the input of ADC, sometimes it works fine and sometimes it gives a fixed code of 00FF (hex). Otherwise the ADC is working fine. Are these limit cycles and what is the solution?

ASIC Design Methodologies and Tools (Digital) :: 02-11-2015 15:56 :: mohd asim :: Replies: **0** :: Views: **525**

Currently, I have designed a second-order **sigma**-**delta** ADC (fin = 20kHz, fs = 5MHz). In this ADC, a 2-**bit** flash ADC was adopted as a quantizer, and a 2-**bit** DAC was inserted into the feedback signal path. The attached file is the system architecture and the simulated results.
113250
According to the output spectrum of th

Analog Circuit Design :: 01-17-2015 04:04 :: davison7 :: Replies: **0** :: Views: **850**

Paper or Thesis information:
T. Thantipwan and N. Wongkomet. "A power-optimized 16-**bit** 1MS/s nyquist-rate **sigma**-**delta** analog-to-digital converter", Chulalongkorn University. To be published.
thank a lot !
- - - Updated - - -
be badly in need of this paper!!!

Analog Circuit Design :: 01-04-2015 07:31 :: wonbef :: Replies: **1** :: Views: **772**

Dear all,
I am trying to design a single-**bit** first order **delta**-**sigma** ADC. The architecture that I am using is the very simple single ended ΔΣ modulator. The modulator is supposed to work for audio band signals (20-20KHz). The clock signal that is used is a 2.56MHz pulse. Therefore OSR is 64.
Switches that i

Elementary Electronic Questions :: 11-25-2014 06:10 :: mmnavidi :: Replies: **0** :: Views: **706**

Hi,
Is there any thumb rule to set the Quantization threshold for generating the **bit**stream while modeling a first order **sigma** **delta** ADC?
I am trying to model a 16 **bit** SDM ADC with a full scale input of of 1Vrms.
Thanks,
Ranand

Analog Circuit Design :: 11-12-2014 09:03 :: Ranand :: Replies: **0** :: Views: **493**

Hi,
I'm a **bit** unclear about a decimation filter used in oversampling data converters. Say in a **delta** **sigma** ADC that has a sampling frequency of 64 MHz, input frequency of 1 MHZ, oversampling equal to (64MHz/(2*1) = 32), and a 1-**bit** internal ADC, the resolution is supposed to be 20 **bit**s. So there would be (...)

Analog Circuit Design :: 10-21-2014 15:28 :: mordak :: Replies: **0** :: Views: **656**

Regarding **bit** true simulation using matlab: is there an "easy" way to model fixed point multiplication that will work transparantly with existing toolkits? Case in point: I recently used the **delta** **sigma** Toolbox (delsig), and it would be nice if you could run the simulation with fixed point multiply accumulate. And same question for (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-23-2014 12:14 :: mrflibble :: Replies: **4** :: Views: **4153**

Hello Everyone
I am working on **delta** **sigma** ADCs in MATLAB, to equalize the amplitude of input and output I have to multiply the output by a scaling factor, anyone who has experience of ADC (using or working on ADCs) share the reason for this scaling ? and Secondly the SNR after **delta** **sigma** Modulator ~66 dB and after (...)

Digital Signal Processing :: 04-05-2013 06:44 :: Eminent.Engineer :: Replies: **4** :: Views: **1102**

Hi daer all;
I have a question that for an 8-**bit** ADC for low-speed industrial applications what is the accepted minimum ENOB for interested bandwidth?
I designed and implemented my **sigma**-**delta** ADC on FPGA; but the ENOB for lower frequencies (20hz) starts from 6.4 and for highest frequency in the bandwidth (8khz) is 4.9 are these values

Digital Signal Processing :: 04-16-2014 03:40 :: membership :: Replies: **0** :: Views: **560**

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antenna feeding network | adc clock jitter | cadence and spectre netlist | patch and gsm | measure theory | keypad pic microcontroller | rom monitor | open loop gain plot | final year project title | package capacitance