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35 Threads found on Sigma Delta Delay
hi I wanted to know that can a sigma delta adc will handle multiple inputs from different source by using a mux
I think they don't spec the settling time because those are probably sigma-delta DACs, not 'normal' ladder types. You could just contact the manufacturer and ask them...
Hey guys, I have a question about continuous time (CT) delta sigma modulators. As you know excess loop delay (ELD) may result in decreasing SNR or even instability. But there is a way to compensate excess loop delay in CT ADCs by adding a second loop and using Dlatch and D flip flops (attached pic). It's from a paper (...)
See a left block diagram in attached first figure. This is a simple 2nd-order continuous time delta-sigma ADC of Feedback structure with a feedback path for excessive loop delay compensation. This compensation path is implemented by DAC3. In this block diagram, I assume passive summation before quantizer. So gain K is required before (...)
What you are describing is exactly what RZ feedback is, but you simply can not just forget about the first 50%. Normally, lets say a really slow CLKed design, you would have your RZ feedback pulse in the first 50% since the Quantizer would be FAST (or small delay)... then zero for the second half. it would still have to be 2X in height compared t
HI I am using AD7705 for Analog to digital conversion in my is 16 bit resolution,2 channel,8 input,sigma-delta Configuration ADC.I am having doubt that how much time(in ms)it will take to change from one channel to another channel (CH 1 to CH 2) or vice versa.Can you please explain with its calculation....
Hello everyone !!!! can anyone tell me why the problem of excess loop delay is encountered only in continuous time delta sigma modulators, and not in discrete time modulators ???? (DAC is present in the feedback path in both the cases)
HI ALL i hesitated if this issue belong to this section but i will be very happy if some one of u will help me i need to create sigma delta modulator for some application. there is any section in the modulator that named noise shaping - it means that after oversampling signal we make integrator loops to the quantization noise and move the quan
I read some papers about the delta sigma modulator and they mentioned the half-delay technology. In the paper, they usually use the switched capacitor integrator as shown in the picture. 58396 What I am understanding is when phi1 is on, the sampling capacitor is charged to Cs*Vi(n*T-1/2*T). And then phi1 is off and phi2 i
Hello guys, I want to build a switch capacitor half-delay integrator for one second order switch capacitor sigma-delta modulator in SIMULINK. Here, the transfer function is z^(-1/2)/(1-z^(-1)). I can use the unit delay model to realize 1/(1-z^(-1)). I know I can use the variable fractional delay model to (...)
hi everyone i am trying to simulate sigma delta adc in simulink. I am not able to understand the function of the integrator block represented by 1/z. It acts as a delay element is ok, but how does it acts as a summer or accumulator. it will be good if some derivation is also supplied.
how to implement non delay integrators in sigma delta adc? for example , in CRFB and CRFF structures of single loop sd_adc.:-(
Hello, I want to design 2-2 cascade delta sigma modulator for 2 mhz signal bandwidth, i must sum the two outputs given by the two stages, i use ORCAD PSPICE for similation, i need to implement H(z) =z^-1 which is a delay unit, i don't know the structure of this function using MOS transistors and how i implement it. Please help me
Dear All, i am modeling a CT delta sigma modulator using simulink , now i am trying to model excess loop delay . I try two methods: 1. use a transport delay but it the delay appears as an increase in the rise time not a delay in the output signal of this block. 2. a D-ff clocked (...)
Hi, my question is about the synchronization between signal delta modulator and decimation filter. The data coming out of the modulator is going to be clocked into the decimation filter. Due to some propagation delay and some interconnect delay, how can the digital clock sample at the middle of each bit duration? What I thought is we can (...)
Does anybody have a simulink file that modeled excess loop delay in CT sigma-delta modulators?
Hi, In the Shcreier book (2004), page 6, it's said that in delta-sigma converters since the signal is unchanged, i.e. there is only a delay for the signal, in the receiver no demodulation is needed and this is a great advantage of delta-sigma modulators comparing with delta modulators. (...)
Insufficient noise filtering of the sigma-delta noise or Frequency downconversion of folding of high-frequency noise because of nonlinearities.
How should I calculate the loop delay in a sigma delta modulator?
That is the paper I am trying to implement,without the half-delay i.e z^(-1/2)...I donno why my SNR stays constant at around 27 dB...I have attached the CT simulink file and the code used to calculate SNR...can anyone please chk