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# Sigma Delta Second

71 Threads found on edaboard.com: Sigma Delta Second

## Coefficients for delta sigma modulator from ABCD matrix.

Hello folks, can anybody help me out how to determine the coefficients(a_i, b_i, and c) from ABCD matrix for second order delta-sigma? I have the values for ABCD matrix but I am not sure which elements are to be chosen for a, b, c coefficients. Thanks.

## [moved] second order sigma delta modulator coefficients implementation in cadence

I heartly appreciate if someone can clarify my doubt on "how exactly the coefficients obtained from matlab are implemented in cadence"

## How to calculate R&C in Sigma-Delta Modulator

Hi I'm trying to use sigma-delta modulator , and I using Altium Design to simulate it , but its response is not good I think I need to change the r & c values but I don't know the equation my I/P signal is Sin wave 80 KHz . 123457123458

## 2nd order Delta Sigma Modulator

I am creating a second order delta sigma modulator for a fractional n pll. First I created the first order one. It worked ok when I removed the output flip flop that had to act as a comparator. Of course there's some sort of comparator glue logic. However it is combinational circuit. I wrote a code in matlab and it worked fine, designed the (...)

## How to calculate a resolution of a delta-sigma ADC?

Hello CHL, While delta-sigma or sigma-delta is in essence an averaging process the oversampling is not the only thing responsible for the ENOB. For example only OSR improves the number ob bits from n to ENOB=n+0.5*log2(OSR). Now this means that for a 5-bit gaing OSR of 1024 is needed. Now if you look at (...)

## Need guidance understanding delta sigma conveters

I need some help understanding delta sigma data converters. Suppose I have a 16 bit delta sigma ADC, a sampling clock at 100kHz and an oversampling ratio of 64. I want to calculate samples per second. A 16 bit converter requires 2^N clocks; 65536 clocks in this case. If my sampling frequency is 1ookHz (...)

## Questions about the noise fllor of the 2nd delta-sigma modulator

Hi~~Everybody, Recently, I have designed a second-order sigma-delta modulator using the CIFB architecture. The fin = 1KHz, fs = 1MHz, and Vin = 1V. In the first, I use the Matlab to simulate its function. The output spectrum shows that the noise floor at dc frequency is about -120dB. But when I use the actual devices of the (...)

## Limit cycles in sigma delta ADC

Hi..... I have designed and fabricated a 16Bit second order, single bit sigma delta modulator based ADC. During testing of ADC, when we apply zero volt at the input of ADC, sometimes it works fine and sometimes it gives a fixed code of 00FF (hex). Otherwise the ADC is working fine. Are these limit cycles and what is the solution?

## Help to check the simulated results for the Sigma-delta ADC

Currently, I have designed a second-order sigma-delta ADC (fin = 20kHz, fs = 5MHz). In this ADC, a 2-bit flash ADC was adopted as a quantizer, and a 2-bit DAC was inserted into the feedback signal path. The attached file is the system architecture and the simulated results. 113250 According to the output spectrum of th

## low pass filter design

hello dear, i generated a target impulse response of fir low pass filter and then interpolated it , now i want to generate ternary tabs or coefficient using second order sigma delta modulation, please tell me how to generate it, if any one have code or idea

## Excess loop delay in CTDS ADCs

Hey guys, I have a question about continuous time (CT) delta sigma modulators. As you know excess loop delay (ELD) may result in decreasing SNR or even instability. But there is a way to compensate excess loop delay in CT ADCs by adding a second loop and using Dlatch and D flip flops (attached pic). It's from a paper published by Shouli (...)

## Sigma-Delta 7715-7730 Maximum Sample Rate

Hello, I working on ADC circuit and i'm new on this topic. I'm trying to design 16 bit ADC circuit with 5000 SPS(sample per second) from input. i have some question. can i use sigma-delta series like 7715 or 7730? what is maximum sample rate of these ADCs? if it is possile, where can i found some information about this design? (...)

## design of second order sigma delta using hspice

hi i need to do design of second order sigma delta using hspice and need help on it.. I HOPE SOME ONE CAN HELP ME WITH THE SAMPLE CODE PLEASE... REQUIRE URGENTLY.. PLEASE MAIL TO: mojtaba.20511@yahoo.com thanks

## Delta Sigma Toolbox in MATLAB

If someone has used delta sigma Toolbox (Scherier or Malcovati) for modeling delta sigma ADC in MATLAB then kindly I need guidance. I want to model second order delta sigma modulator and decimation filter in MATLAB with non-idealities and couldn't know how to utilize these (...)

## sigma delta modulator design in verilog-A

iam working on the verilog-A modeling of first and second order DT sigma delta modulator in synopsys custom designer. verilog-A code for filter is shown below : module filter(vin,vout); input vin; output vout; electrical vin, vout; parameter real n0 = 1.0; parameter real T = 7.8125e-7 from (0:inf); parameter real t = 2n from (

## problem in verilog-A model of second otder sigma delta modualtor pls help!!!

iam working on the verilog-A modeling of first and second order DT sigma delta modulator in synopsys custom designer. verilog-A code for filter is shown below : module filter(vin,vout); input vin; output vout; electrical vin, vout; parameter real n0 = 1.0; parameter real T = 7.8125e-7 from (0:inf); parameter real t = 2n from (0:inf);

## sigma delta modulator simulation using simulink

We r working on second order sigma delta modulators. We have created a model using simulink. But we r getting error with sampling time parameter in each blocks. we are not understanding where to change the sampling frequency in the model. also can anyone suggest how to plot logarithmic PSD in will be really greatful if you help us. Th

## filter section in delta sigma ADC

In the 2nd order sigma delta (mesh architecture) document "ROBERT AND DEVAL: second-ORDER INCREMENTAL A/D CONVERTER" , up-down counter approach to implement filter section (page 738 and 739) the filter stage1 after comparator 1 uses x = x + xx * (n - i +1) where xx is comp1 output and x is output of filter and 1

## CT Sigma delta ADC-CIFF-2 order

signal BANDWiDTH is 25 khz...n my sampling frequency is 100 MHZ...i need to determine R and C values of integrator... for the first and second integrator confused in choosing them.... and how abt the constraints on first and second OTA of on gain n bandwidth.... can u plz help me out R and C values of using SCR feedb

## second-order Sigma Delta Modulator

Who does the second-order sigma delta Modulator and the second-order sigma delta Modulator non-ideal modules can be provided to me for