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166 Threads found on Sigma Delta Simulation
Hello, I've read around extensively about FFT setup for a sigma delta ADC and I'm not sure if I'm not setting it up properly . my current setup for a first order sigma delta ADC sampling frequency : 38.4 kHz (for the ADC and FFT setup) FFT bins : 65536 input signal : (31*38400)/65536 = 18.1640625 Hz I'm using (...)
hi all, is there any system Verilog code for a 1 st order sigma delta modulator?
Hi everybody, I have a couple of questions about power spectral density simulation of the sigma-delta modulators. I want to see the harmonics inside the output bit-stream of the modulated signal. The details of what I did are provided at this link: I will be so thankful if you answer these questions: 1- How lo
Hi All, I'm simulating a transistor level, continuous first order delta sigma modulator and need some clarification on the my gm-c filter. simulation is all in Cadence. The input frequency of the DSM is 10hkz so what should the 3-db cutoff frequency (not my unity gain frequency) of my gm-c be? I was thinking that my f_3db should at (...)
The op amp with the ideal vcvs in the CMFB circuit still affects the sigma delta ADC performance greatly!! Could you show how you connected the vcvs-CMFB to your opAmp?
I am designing a 3rd order sigma delta ADC, with 1.5 bit comparator, i modeled the system using ideal components and the system worked as expected. Now, i inserted the comparator i designed (CMOS Comparator), while simulating , i got confusing results When i simulate and calculate the FFT (or DFT) using 4096 points, the output is as follows yie
Hello I have some queries about delta-sigma DAC. 1) basically, it is same with delta-sigma ADC, but it consists of digital blocks, such as accumulators. However, how to synchronize the clock with PCM signals from a DSP? Does it need serial communication circuits? 2) I tried to find Simulink (...)
Hi All, This is my first ADC and verifying it is proving to be more difficult then actually designing the subblock. I have been able to do a transient simulation in cadence (spectre) and have successfully imported the data into matlab. This is where I'm encountering most of my headache. 1) I'm new at matlab 2)All of the fft examples I've
Hi, I'm working on a project about audio sigma . There are some spurious components in audio band(20Hz~20KHz) when the ADC is stimulated with no signal or small amplitude signal such as 10mVpeak-to-peak 1kHz audio signal while no other analog or digital modules can generates that low frequency (such as 2.3kHz, 10kHz) components on the same chip.
3rd order sigma-delta has various configurations. please study following texts: "A Third-Order sigma-delta Modulator with Extended Dynamic Range" by:Williams "Continuous-Time sigma-delta AD Conversion" By:Ortmanns "Understanding delta-sigma Data Converters" (...)
Regarding bit true simulation using matlab: is there an "easy" way to model fixed point multiplication that will work transparantly with existing toolkits? Case in point: I recently used the delta sigma Toolbox (delsig), and it would be nice if you could run the simulation with fixed point multiply accumulate. And same (...)
Hi,everyone! I have built a 3rd order feedforward delta sigma modulator in spectre, the fully differential opamp, comparator, d_ff are all implemented by veriloga model, while the switch are CMOS transmission gate. My question is the SNR calculated from the spectre output is only 33dB, while in Simulink the SNDR is 103dB, i don't know how to sol
There are different sources of non-linearity in a SD-modulator. The assumption, that you mainly see odd harmonics is of course based on prerequisites, generally speaking no even terms present in the polynomials describing the transfer characteristics of individual building blocks. There's a paragraph about distortion in the simulation chapter o
i've done some simulations on sigma delta ADC. but i think my output is not so correct..anyone can help me out attacedh are my design and waveforms mainly the decimation design im not sure of. matlab simulink 1st order sigma delta adc input: 2V Fb=1kHz , OSR=16 times88922 the 1 bit DAC simply is (...)
have anyone done any simulation of the DSM . here is my design.. but my output seems to be inverted.. anyone know if im doing anything wrong or can explain to me why my waveform is inverted. 89268 my output bit steam when input at Vmax there should be more 1s at the top however my waveform stated otherwise. [ATTACH=CO
Hi, Because i have obtained with Malab simulink simulation the same signal ouput as in the input. I need to design decimation filter in VHDl code for this simulink sigma-delta anlog to digital converter. osr=64 = 16 * 4 Fs=10.24MHz fb=80Khz nb=8bits here i design the decimation with two sinus cardinal "comb?filter" (decimation of (...)
I am building sigma delta ADC, i want to include the effect of thermal noise in the sustem.. Is there any way to include noise source to represent resistors' thermal noise ?? a random source generator or something ?
first of all u need u understand the modulator portion. it consists of 1. Loop filter which is basically an integrator in discrete time ie z tranform so u need to know about z transfroms and then how to create a filter in z-domain 2. Quantizer which is basically is 1 bit comparator which can be implemented using sign block in Matlab Simulink 3. DA
I want to model an sigma delta ADC with VHDL. in this case we ned to have an LowPass RC. and for simulation also we need its model. 78976
hi all I design sigma delta modelator by matlab and hspice but output of noise shaping not correct in hspice!!! there are images of noise shaping outputs. can help me? [img