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166 Threads found on edaboard.com: Simulation Delta Sigma
Hello, I've read around extensively about FFT setup for a sigma delta ADC and I'm not sure if I'm not setting it up properly . my current setup for a first order sigma delta ADC sampling frequency : 38.4 kHz (for the ADC and FFT setup) FFT bins : 65536 input signal : (31*38400)/65536 = 18.1640625 Hz I'm using (...)
This might be a typical university exercise. I remember in our 1st year our professor had given us the assignment to develop a VHDL model of a sigma-delta converter. It was required just to work in simulation, no synthesis. I don't remember anything further after so many years. ;-)
Hi everybody, I have a couple of questions about power spectral density simulation of the sigma-delta modulators. I want to see the harmonics inside the output bit-stream of the modulated signal. The details of what I did are provided at this link: I will be so thankful if you answer these questions: 1- How lo
Hi All, I'm simulating a transistor level, continuous first order delta sigma modulator and need some clarification on the my gm-c filter. simulation is all in Cadence. The input frequency of the DSM is 10hkz so what should the 3-db cutoff frequency (not my unity gain frequency) of my gm-c be? I was thinking that my f_3db should at (...)
You should be able to see in a simulation which real OP parameters have the greatest impact. I guess, low gain will be a problem.
I am designing a 3rd order sigma delta ADC, with 1.5 bit comparator, i modeled the system using ideal components and the system worked as expected. Now, i inserted the comparator i designed (CMOS Comparator), while simulating , i got confusing results When i simulate and calculate the FFT (or DFT) using 4096 points, the output is as follows yie
Hello I have some queries about delta-sigma DAC. 1) basically, it is same with delta-sigma ADC, but it consists of digital blocks, such as accumulators. However, how to synchronize the clock with PCM signals from a DSP? Does it need serial communication circuits? 2) I tried to find Simulink (...)
Hi All, This is my first ADC and verifying it is proving to be more difficult then actually designing the subblock. I have been able to do a transient simulation in cadence (spectre) and have successfully imported the data into matlab. This is where I'm encountering most of my headache. 1) I'm new at matlab 2)All of the fft examples I've
Limit cycles and and some spurios compnents are generated by design and can be reproduced in a simulation with ideal circuit elements, other interferences are caused by non-ideal hardware properties. You should be able to sort out which kind of interferences shows in your case.
3rd order sigma-delta has various configurations. please study following texts: "A Third-Order sigma-delta Modulator with Extended Dynamic Range" by:Williams "Continuous-Time sigma-delta AD Conversion" By:Ortmanns "Understanding delta-sigma Data Converters" (...)
A model is just a model - it doesnt matter how you implement it. If it is bit-true to can treat it as a black box - so you put the same data through your model and FPGA code and you should get identical results. The FPGA code needs to be written in VHDL or verilog. Either hand written or generated. Simulink has an HDL coder addon that can take a s
I would suggest you extend the transient simulation time so you have at least 2^16 samples of BS. Export the BS and do an FFT. For example with a 2 MHz clock for 2^16 you need a simulation time of aprox. 32.8 ms. BR Jerry
There are different sources of non-linearity in a SD-modulator. The assumption, that you mainly see odd harmonics is of course based on prerequisites, generally speaking no even terms present in the polynomials describing the transfer characteristics of individual building blocks. There's a paragraph about distortion in the simulation chapter o
i've done some simulations on sigma delta ADC. but i think my output is not so correct..anyone can help me out attacedh are my design and waveforms mainly the decimation design im not sure of. matlab simulink 1st order sigma delta adc input: 2V Fb=1kHz , OSR=16 times88922 the 1 bit DAC simply is (...)
have anyone done any simulation of the DSM . here is my design.. but my output seems to be inverted.. anyone know if im doing anything wrong or can explain to me why my waveform is inverted. 89268 my output bit steam when input at Vmax there should be more 1s at the top however my waveform stated otherwise. [ATTACH=CO
Hi, Because i have obtained with Malab simulink simulation the same signal ouput as in the input. I need to design decimation filter in VHDl code for this simulink sigma-delta anlog to digital converter. osr=64 = 16 * 4 Fs=10.24MHz fb=80Khz nb=8bits here i design the decimation with two sinus cardinal "comb?filter" (decimation of (...)
In the standard noise simulation, ideal resistor noise (calculated from its resistance value) is included (there may be an option to select/deselect it). Same is true for all the devices, if their models include the corresponding parameters.
hi anyone around can help me with my digital portion.. i've been stuck for 2 week unable to get my decimation filter up .. need advice and guidance and examples if any of u have.. really appreciate8527185272 simulation stop time = 0.03 input sine signal = Amp= 12, Freq=2*pi*60 C
I am looking for "rc low pass filter" model for simulation in vhdl. Is there any link or guide?
hi all I design sigma delta modelator by matlab and hspice but output of noise shaping not correct in hspice!!! there are images of noise shaping outputs. can help me? [img