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Simulation Timing Check

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48 Threads found on edaboard.com: Simulation Timing Check
I have finished synthesizing my circuit in design compiler. Now I want to do a gate level simulation in Modelsim in order to get the power consumption. The gate level simulation works correctly, but generates "xxx" when annotated with the SDF generated by design compiler. I've tried to reduce the clock frequency but still get the same result. I sho
The simulator runs as fast as your computer lets it. The simulation times are accurate but not real-time as mdorian stated. To check the program simulation running time, use 'Debugger/Stopwatch' from the menu bar. Make sure you reset it if you are timing the delay between different parts of the program. It is very useful (...)
When doing gate-level simulation with SDF annotated, we can use options to tell simulator use minimum, typical or maximum values specified in file.sdf be annotated on the design. My question is, does this option effect which value (min/typ/max) should be used for timing check in SDF? For example, if there are below two lines in SDF: (...)
Sir, I have generated netlist for a 16 bit counter using Encounter RTL the synthesis I set the clock as define_clock -period 3500 -name clk and in the timing report generated a have a positive slack - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock clk) capture
HI actually its not possible to post code....... Why not, I'm primarily interested in the testbench and the portion of the design that distributes the clock that drives the first register that gets data. If my theory is correct you've got data that is captured on the same edge it transitions. e.g. [FONT=Co
STA does not check any functionality. Gate simulation with timing of the scan, will confirm that the model used for analog-pad... are correct, and the timing checked during STA is also align.
The simulation problem is caused by 1 ms "Minimum Trigger Time" of Display model. I didn't check if the display timing is suitable for real hardware.
What do you mean "after verification"? Good question. Sorry, let me frame the question again: Why are the to do LEC on top of RTL verification and gate level simulation in a digital design cycle? Regards
We are doing simulations without timing to check that the pattern generated is properly working or not.... with timing simulation purpose is to check that SDF is proper or not means timing closure is working well or not... After fabrication, design is working in serially so (...)
Hello, I've been trying to calculate average power with PrimeTime PX. I designed a simple FF in Verilog and synthesized it with DesignCompiler Topographical mode. After synthesis, when I simulate the netlist with SDF annotation, I've got following warnings. ================================================================================
Well for simulation, the verilog RAM model are usually quite simple to understand and to check versus the data sheet. Could you clarify which RAM verilog model you used for synthesis? the synthesis tool need a liberty file, no? And the liberty file is also "quite" simple. A liberty describe timing arc between i/o which also available on (...)
Hi all, suppose that I have a block whose task is adding 1 to its input and output the result after 1 clock delay; also suppose that the behavioral simulation worked just fine. If the post-PAR (timing simulation) shows a different result, i.e. that the result comes out after 2 clock delays (see the attached figure), what could be the (...)
Please check the simulation setup is not pessimistic compared to synthesis setup. Other way to ask you Is simulation setup matching with synthesis setup.
Hi, I am simulating the pattern generated by tetramax in ncverilog. I have used no timing check off. This is just a basic scan chain shift test. My chain is failing right from the start ...with the below message : Netlist : {dc generated} >> Error during scan pattern 1 (detected from unload of pattern 0) >>> At T=637315.00 ns, V=6374,
I have seen couple of posts on this forum as well as where people have suggested disabling timing check during gate level timing simulation. My point is what is the use of gate level timing simulation, if you disable timing check? It is true (...)
Can anyone suggest me how to debug for simulation mismatches in gate level atpg. What are the usual sources of error one need to check first
Someone said that the SDF gate simulation will check the false path is correctly setting in the timing constraint(.pt). But I think it's not reasonable because in the test bench, the clock generation is different with the clock setting(synchronous or asynchronous) in the timing constraint. So the gate (...)
I tried report timing -to > timing.rpt, but in the timing.rpt, I still got one critical path timing. Actually, I want to know every gate load capacitance the RTL complier used for a big circuit. Then I can check the accuracy of NLDM w.r.t. spice/spectre simulation. is there any (...)
Hey Sun_ray, During Static timing Analysis (STA), design functionality is "NOT" checked, only timing is checked to see if it meets the timing specification. That is why gate level simulation is done with timing to see if functionality is correct with (...)
gate level simulation is done mainly to check for timing. The main tool for timing is static analysis. gate level takes very long time to run and usually comes as a second measure covering partially of the timing. So one gains confidence in the STA assorted assertions he made as well as of the synthesis (...)