Search Engine www.edaboard.com 64 Threads found on edaboard.com: Simulink Sample

## How to simulate in Simulink the FFT of "Sample-and-Hold"

There should be better alternatives to fix that issue, but the only one I see based on my previous experiments, could be by replacing all the stuffs before S/H blocks by an 1-D vector, in you case with the length of 4096 values. Don't know exactly what function could do that, but discretizer is the first one which

My ADC structure uses a loop and I do not know why simulink complain about it. I have the following situation: I have a sample and Hold (SH A) cell controlled by a combinational logic and its output is used as input in another sample and Hold cell (SH B). Besides that, SH B's output is used as one of the input that control SH A's clock. (...)

## GCC-PHAT based time delay estimation

Hu guys! Anyone could help me solve the following problem. I try to simulate time delay estimation in simulink based on GCC-PHAT method (see Fig1 for explanation). My FFT is correct as I checked it but I'm not sure why I can't get the correct sample delay (in this case 15). My simulink model is shown in Fig2. Any advise and help will be (...)

## Problem with SNR AWGN Channel simulink OFDM

Let's say that we have a random integer generator with sample time Tb/samples then we pass through modulation and we meet the awgn channel.We set it at SNR mode.I need to understand how the given snr relates with signal power and the variables i ve already mentioned.How can i compute them properly in order to get the correct ber? THANKS I

## Measuring power of a data signal in SIMULINK

I am using a Bernoulii Binary Generator to generate my data signal for a Direct sequence spread spectrum model I am designing on simulink. The specifications of the generator block is as follows : Probability of zero : 0.5 Initial seed : 61 ( random number ) sample time : 0.6 Frame based outputs samples per frame : 100 I wish to (...)

## sample-based simulation in simulink

hi i am trying to find a way to make a reed-solomon encoder block in simulink function in sample-based mode. i am also trying to find a way to take a stream of randomly generated integers and form 1x188 vectors with out using the buffer block, that i can send through a reshaper block to input into the reed-solomon encoder block. i have many more

## setting of simulink time period and sample period

hi i am a new in fpga programming so if anyone could help me out in clearing this confusion between simulink clock period,fpga clock period(sysgen token) and sample period in respective blocks of the design???? for example if my starter board spartan 3 has a clock oscillator of 50 Mhz so will my fpga clock period be 20ns or something else? i

## IIR not working on system genrator

Im trying to implement 2nd order IIR filter ( direct form 1) by xilinx block set in system generator but on output im getting noise. same filter i implemented in matlab simulink (without using xilinx block) it is working fine. I checked till feed forward path the output of matlab simulink and system generator both are same. i think that some p

## Find Pulse Width in Simulink

Hello I'm trying to find the duration of a pulse of an incoming PWM. I'm using simulink for that. First I tried to use a counter to count microseconds between rising and falling trigger. It worked great on simulation, but when I tried it on external mode (as I need this model to be), the sample time just killed the model and the time of t

## question about sampling

hello all, i want a help to know how i can sample measured signal in simulink and know the values of these samples......thanks for all

## Simulink implementation of the product block with alternating multiplicand sign

Hello everyone !!!! I am trying to implement the "Double-sampling capacitor mismatch modeling" given in the paper (page 3) attatched with this post. Can anyone suggest me how to implement the the model in simulink??? I dont know how to implement the product block with th multiplicand changing sign after every sample... can anyone kindly h

## HDL simulink: DVB-T OFDM pilot insertion/cyclic prefix

That's my first thread in this board, so hi all :) I'm realizing an HDL synthesizable model with simulink. I'm facing problem with blocks that needs an output sample time higher than input like - pilot insertion: from a continuous stream of data i should insert samples from a sequence (ex: in 2k-mode, every 1512 data input i should insert (...)

## Error running simulink model for Mb ofdm uwb system

Hi,when i run my simulation modelled by simulink and matlab it displays an error" The periodic sample time 1 is not allowed because the ratio of this sample time over base rate (1.01010101010101e-014) is greater than the maximum value of uint32".Can you please help how to fix this problem?Thanks a lot!!!

## MB-OFDM UWB simulink simulationCan any one help.When i run my simulation f

Hi,when i run my simulation modelled by simulink and matlab it displays an error" The periodic sample time 1 is not allowed because the ratio of this sample time over base rate (1.01010101010101e-014) is greater than the maximum value of uint32".Can you please help how to fix this problem?Thanks alot!!!

## Need startup help on Xilinx System Generator

Hi all, I want to start some work on the xilinx system generator in simulink, any ideas or tutorials/sample projects on where should i start?, also when i made an inverter in simulink using the system generator, it compiled in matlab just fine, but when i try to simulate it in Xilinx ISE, it gives errors and makes like 7 inverters in (...)

## Integrate and dump block

Integrate and Dump Block in the Communications Blockset in simulink introduces one sample delay in the output... Is there any way of removing tat one sample delay... Since I use a buffer(of size 48) after integrate and dump, Iam facing problems because tat one bit delay introduced by integrate and dump affects the frame 0f 48x1 that comes (...)

## rf frequency downconverter mixer in simulink

Hey all, I'm trying to model a frequency downconverter mixer on simulink. The input is 2Ghz mixed with LO=1.96G. the sample time i put is 0.01e-9 and the solver with a fixed step. unfortunately the output frequency is the same as the input frequency. I attached the model. Can anyone help? Thanks

## reed solomon code using mary fsk using simulink in matlab

how can i set frequency separation and sample per symbol in M-fsk modulation in designing reed solomon code using simulink? Is there any relation between symbol period of AWGN channel and mary fsk modulation? And as i am doing comparision of different reed solomon code keeping code rate constant,is it necessary to keep mary fsk techniue same

## continuous Time VCO block in MATLAB SIMULINK.

Hi, I am trying to understand the functioning of continuous Time VCO block in MATLAB simulink. Can you help me out see the variation in the output frequency as I sweep the input voltage. 1. How to do a DC Voltage sweep in simulink? 2. The input of a Continuous time VCO BLOCK needs a sample based scalar. What does that mean? 3. Can (...)

## Sen data from simulink to workspace

Hi everyone I want send a boolean data to workspace from simulink,for example i want get data from simulink A=1 or A=0 in workspace after runinig simulink.I know simout block but this block send data to workspace in form of Array,Structure or Structure with Time that it isn't my sample frequency is 1MHz. I need your help (...)