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Hello! I need activate load when ttl 3v input low. Is attached shematic will work good?157939
Hello everybody, I have been trying to simulate the design of a CPW using HFSS and I would like to analyse a little bit more the losses mechanisms in the simulation. For that I have been trying to compute the losses due to the finite conductivity of my metallic electrodes (defined as volumetric objects and allowing the solver to solve inside of
I've been doing a lot of survey article for fanout for design compiler. But for some technology process such as 90nm/.18um , our target library (.db / .lib) has already the settings of max_fanout/ max_capcitance for our design, but in 4x nm process, I can't find the max_fanout in .lib file 1. Is that the reason for settings ?? (But how to determi
Why is csh/tcsh shell still used as default shell in IC design industry when scripting in cshell is so frowned upon. Is shell scripting still around or has been completely superceded by languages like perl/python. Being a fresher in this industry which shell does it makes the most sense to go for, bash or csh.
Hi, It is said that timing should be checked even on the metal-filled gds since the metal fill can have some effects on the timing of the design. How are these timing checks carried out, in which tool ? Can you please elaborate ? Thanks, Aditya
Hi , At the moment I am trying to perform parasitic extraction using PVS-Quantus to get the RLC parasitics of the metal stack (routing). the Pcell of my the transistor already includes RLC parasitics , I want this part of the layout to be blocked from parasitic extraction to avoid parasitics double counting To do that : ? I preserved the
Hi all, I really got stock on doing phase noise simulation for a PLL model made in MATLAB simulink ? DO you have any guides or tutorial ? Thank you. I appreciate.
I am trying to replicate a 4 X 4 butler matrix How should I emulate the MIMO encoder and decoder in Sonnet
Hey guys.When is a solder with silver content used?
In this case ".elf" is generated for a arc processor from a synopsys metaware IDE SDK tool. I want to convert to .bin or particularly .hex file so that i can use it for a verilog memory initialization file ($readmemh) and do some simulations. Thanks
I recently got TI control card for F2837X cpu ( ) I am using CCS as an IDE. I am trying to first understand how to flash a simple LED blink program to the board and debug it. But struggling with it. I connected the control card to computer with USB c
I want to model a complete PLL behaviourally and use MATLAB with an arbitrary VCO phase noise profile. My VCO has a known KVCO and a known Phase Noise at a 1MHz offset (say 130dbc/hz). I also know the VCO noise floor (say -140dbc/hz) and that it has a 1/f^3 dependence elsewhere. How would I model this VCO in MATLAB for a MATLAB/simulink simu
Hi , At the moment I am trying to perform parasitic extraction using PVS-Quantus to get the RLC parasitics of the metal stack (routing). the Pcell of my the transistor already includes RLC parasitics , I want this part of the layout to be blocked from parasitic extraction to avoid parasitics double counting To do that : ? I preserved the
Hello. I am working on a project to improve wifi strength of an android tv box in a classroom. It comes with a 50 ohm dipole antenna. In the classroom, the router or repeater is situated in the rear of the classroom. I proposed replacing the antenna with a transmission line fed patch antenna. Simulation indicates 7.14dBi directional gain compare to
Hi everyone, For a project involving multiple drones communicating to a single base station, I'm looking for a chipset (or alternatively a module) that supports a star topology network (i.e. multiple transmitters sending data to a single receiver). I need quite a bit of range (about > 2 km) with antennas that aren't ridiculously large since they
Hi, To implement an RC low pass filter at a (window) comparator input that is buffered by a voltage follower op amp, the window comparator purpose is to control an LDO enable pin and only take it high between 0C and +45C, what might be a realistic RC LPF value to avoid comparator chatter if hysteresis isn't used? Would ~3.3 Hz (0.29s) be okay
I am trying to do a two element matching. When I try to place a SmithChart component into my schematic, I get the following warning: WARNING: ads_work_kangaroo/%D0X0.07FFC1F1B057P-1022_(null)mith hart%Match_cell_1/itemdef.ael AEL file not found[/COLO
Hi, I have connected a capacitor (C) in series with the gate of a mosfet(M, let's say a CS amplifier). It's value (180 fF) is not too high like a blocking capacitor. How does increasing or decreasing this value change the output power and lower(input) cut-off frequencies?. My analysis is like If the C value is decreased, the Vgs of M decreased b
B4A is a RAD tool for developing Android software. It is similar to Visual Basic with a lot of the same syntax and structure. It hides all the JAVA in an easy to use package. The development software has just been made free to use. It appears to be the full version and is not limited in any way. B4A: https://w
I'm trying to use smith tool in HFSS to get a matching network. Every time I try to open smith tool, the program aborts. Has anyone encountered this? Any suggestions?