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12 Threads found on edaboard.com: **Slope Calculation**

A few questions:
1) Why do you think the **slope** would be 45 degrees? The **slope** in the standard ω-κ format should be c, the speed of light.
2) Why are you using PECs on one side and PMLs on the other? PMLs should only be needed where an open boundary (which accepts radiation) is required. Since your plane wave will be propagating betw

RF, Microwave, Antennas and Optics :: 11-04-2016 14:22 :: PlanarMetamaterials :: Replies: **7** :: Views: **891**

Hello,
today I saw an book to describe the modeling of power switch for dcdc.
for me there is a question that about the **slope** value **calculation**:
* for the buck, it is obviously that the up **slope** is S1=(Vin-Vout)/L
* while from the book, it is expressed as S1=Vac/L
I am confused about this equation, and does any one can help me to (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 07-28-2014 15:08 :: dyjguilin :: Replies: **0** :: Views: **373**

Howsit guys,
I have built a dual-**slope** integration ADC using an integrator and schmitt trigger( for zero detection) for a power meter, I need to pass the output voltages ( analog) from the current and voltage sensors to a pair of ADC's that I built using analogue components such as CMOS switches, inverters, etc. These ADCs incorporate dual slop

Analog Circuit Design :: 09-22-2012 12:21 :: Fe(II)man :: Replies: **2** :: Views: **1213**

SR+ =229e6.
SR- =-227e6
CL=1pF
but these are very high values right ....??
have i done any mistake in **calculation** of maximum **slope**??
SR+ =229e6 = 229 V/?s which means 7.64ns for your 1.75V step. Zoom into one of your step edges and verify!

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-18-2011 10:29 :: erikl :: Replies: **5** :: Views: **2211**

Hi
I need advices on noise **calculation** of ADC.
I'm designing a single-**slope** serial ADC. A two-stage comparator compares Vin with Vramp and drives an NAND-gate. The output of the NAND gate then activates a counter. The counter operates at much higher frequency than the -3dB freq of the compartor.
I want to calculate the thermal noise of t

Analog Circuit Design :: 11-29-2009 02:56 :: noleeach :: Replies: **0** :: Views: **1883**

Hello!
Is this a question?
Is it part of your math homework?
Dora.
dx(t)/dt denotes the **slope** of the signal x(t), obtain an expression for the highest allowable **slope** of the signal in terms of modulation parameters (modulation frequency and step size)
And explain two possible methods to prevent from the **slope** overloading

Digital Signal Processing :: 06-30-2009 00:26 :: doraemon :: Replies: **1** :: Views: **681**

Hi
Must be a small question.
I wan to know how to impliment Two point calibration and **slope**/Offset **calculation**.
ExampleL
If you have a temperature sensor and you like to calibrate it with two know temperatur levels. There must me some error or difference in the known values and the value given by your sensor.
in software calibration the soft

Microcontrollers :: 08-21-2007 09:16 :: sadat007 :: Replies: **0** :: Views: **4204**

If its linear, and you have two points, namely, thinner doping and thicker doping values, make a line and find its **slope**. X-axis is the distance. Y-axis is the doping profile.
I am not too sure about my answer, but the reason I think its not a bad method is because the gradient is in cm^-4, which is (cm^-3)/cm. Kinda reverse answering..
If an

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-15-2006 03:47 :: srivatsan :: Replies: **1** :: Views: **2103**

Hi,
In the opamp design, first u assume the amount of current to flow at the tail, let say about 100uA. Then to find out the value of λ, take a single PMOS or NMOS. You fix the gate voltage and u sweep the VDS (Drain voltage). Later you plot the curve IDS Vs VDS. So, you can measure the value of ro (output impedance) from the **slope**. Then co

Analog Circuit Design :: 10-11-2005 10:08 :: suria3 :: Replies: **5** :: Views: **1306**

I want to plot the gm curve in HSPICE. Using the DC sweep Id vs Vgs can be plotted, so now is there a way to plot the **slope** of the curve also??

Analog Circuit Design :: 06-02-2005 07:08 :: aryajur :: Replies: **5** :: Views: **8100**

It can be runned .Tran analyse with a slow and **slope** input. It also run .DC analyse and sweep vin.

Analog Circuit Design :: 05-29-2005 09:10 :: staric :: Replies: **4** :: Views: **5655**

Srivats..
...please remember following 2 rules for current mirrors..
1. always use Channel length which is 4-5 * Lmin ...(though this is ideal for DSM i.e < 0.25u)....the best thing wud be for u to characterize the MOS and see for which 'L' Id **slope** is less...use that length
2. Ensure that Vds of mirror X'tors are similar..this takes out (1+

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-09-2004 08:03 :: airace :: Replies: **9** :: Views: **1392**

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