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30 Threads found on Smps Zero
Hello, The following two LTspice simulations are almost exactly the same (both full bridge smps?s)?They have the same NP/NS value, but slightly different primary and secondary inductance values. Everything else is the same about these smps's. So why does the one with lower primary inductance have a higher output voltage? (316V versus 301V)
A better Bang for the Buck (intended pun) is to design a low voltage drop linear regulator after the buck smps which maintains the constant low voltage drop, while the linear regulator minimizes the ripple and has the benefit of current limit control down zero with wide BW ripple rejection and low step-load regulation error. In the old days Lambda
Do you agree with the following ?rules? (A to D) on the checking of type 2 compensator pole and zero positions? This is with regard to a CCM, Current mode flyback with a type 2 feedback compensation network..That is, making sure it is not going to be unstable.. ?The Type 2 compensator zero MUST BE at (or very near) the same freq
Hello, In a current mode flyback, compensated with a type 2 error amplifier, it is a fact that the error amplifier's high frequency pole should always be at a lower frequency than the frequency of the power stage ESR in order to assure you avoid instability Is this true? ie, ensuring the above won't assure stability but is a good and
it means that you have an smps where as soon as the inductor current falls to zero, the driving voltage is again forced across the inductor and the inductor current begins to build up again. So the inductor current falls to zero , but does not languish other words, the inductor current is triangular and not trapezoidal, and there are n
Hi all, Designed Flyback Topology based smps.Now want to convert smps in to zero Voltage Switching Flyback smps. How to design ZVS Flyback Converter? Thanks & waiting For Knowledge Enhancement,:thinker: Sachin
As most smps models, the paper is using an continuous time equivalent circuit. In most cases, the average delay of the pulse width modulator is a major contribution to loop delay. It's a systematical rather than a non-ideality parameter. 3.) Other models show there is a zero due to the output capacitor ESR. In the formula however it doe
The following (attached) is a 250W full bridge smps as used by a huge Telco in a PSU. Spec is fsw=300khz, vin=48v, vout=26v,current mode, CCM , Np/Ns = 1 The main cout cap is C54 (68uF) and you can see it has resistor R37 (220mR) in series with it. Why is this resistor there.? Why would you want to decrease the ESR-Cout zero
Hello, I thought LLC converters were supposed to have zero voltage switch_ON and Switch_OFF of the FETs? However, as this waveform view of VDS (red) and I(FET) (green) shows, it definitely doesn't have zero voltage switch off. Why is this? LTSPICE simulation and schematic attached By the way, the
Hello, The below Half Bridge smps simulation, has a transformer turns ratio of 1:0.616 Vin = 400V If the transformer leakage is made zero (coupling factor = 1), then the output voltage = 67V If the Half Bridge transformer coupling factor is made to a more realistic value of 0.99, then the output voltage is just 46V (even though the dut
Hello , I am doing a offline flyback (Pin=16W), (Vin=230VAC) (Post mains rectifier capacitor = 330nF.) Page 7 (equn 2) of the following gives the voltage variation on the post mains rectifier capacitor. However, how do I calculate the "dch" value. Since I only use 330nF, "DCH" will be large, but I
How can you possibly expect to make a smps welder with zero knowledge about smps. I see smoke in your future.
Hello, I am doing a 45W, DCM flyback (isolated) with 90-265VAC mains input. (Vout = 25V) The feedback is optocoupler based. When the electrolytic capacitors in the output get older and have a greater ESR, this will reduce the ESR zero in frequency. Will this mean that its likely to go unstable? Or will the reducing ESR zero frequency a
Hi i am new member in this i am repairing of astec smps model number sa451-3500,but i have problem i.e when we switch on the power supply the outputs comes (+5v,+12,-12v,+3.3v,-5v,-12v) then all outputs goes to zero please help me what is the problem in the smps...i allready checked all passive and active components and (...)
The harmonics from a 12Vdc-230Vac modified sinewave inverter, is giving me the odd harmonics. 50Hz,150Hz,250Hz. If i change this voltage back to DC with a smps, is it possible that the rectifier changes the harmonics to the even harmonics of, 100Hz, 200Hz,300Hz? I don't understand the question. You mean convert
Almost certainly not. Standard smpss never have isolated outputs, which is what they would need to be. The outputs are already 'joined' at the zero (ground) and trying to join them in any other way would not be good!
When you connect a lamp load to an smps the cold resistance is zero.(shorted)The smps is short ckt protected and goes to shutdown. However adding a series choke EI33 to the lamp gives a passive impedance reflected to primay winding of the smps limiting the current slope of the primary current in the mosfet device . The DC to (...)
Hi, The Half-Bridge smps is a zero-Voltage-Switch-ON converter. -Because when a FET turns off, the primary magnetising current continues to circulate, and does so by forward biasing the opposite FETs parallel diode.... ...then when this FET is turned ON, it obviously has zero volts across it , because its diode is conducting. So (...)
hi all So i have a problem with a power supply of echographe aloka the problem is when i start the power supply all is ok , all output voltage are ok but this is take for a three maybe tow second and then it slow down to zero (all the outputs) until the 400v capacitor discharge complitely. i think for the first time that the control is not
I came across this sentence which I couldn't understand at all. Help me " Ideal switching elements (e.g., transistors operated outside of their active mode) have no resistance when "closed" and carry no current when "open", and so the converters can theoretically operate with 100% efficiency (i.e., all input power is delivered to the load; no

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