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Snr Comparator

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9 Threads found on edaboard.com: Snr Comparator
Hello everyone, Can anyone tell me the reason for the invariance of snr of a single-bit sigma delta modulator with comparator offset. ?? U can also suggest the necessary reference.
Hi. I must to design a cyclic ADC and after few weeks I found that my comparator has an offset error so I want to test this parameter with Hspice. at first i design a 3-bit flash ADC with Hspice but amount of SINAD that matlab show me is incorrect and give me about 22db. can you help me to correct this error and can you recommend a right for
To recover the carrier from a quadrature modulated signal, you need to know the modulation scheme and an unique property that allows to decide about the carrier phase. The effort depends. I don't expect that a comparator serves the purpose in most cases. If it does, the achievable snr will be considerably worse than with a recovery algoritm usin
For best snr, you would want it to be as large as possible. However, you are constrained by things such as error amp output swing, ramp generator headroom requirements, comparator input swing etc. With a larger ramp, the impact of non-idealities such as error amp and comparator offsets will also be reduced.
1) DNL is affected due to comparator offsets and due to gain error of the opamps in the mdac sections. the INL is just a cumulative sum of the DNL. the snr, THD are frequency content parameters. the finite gain and bandwidth of the ota in the mdacs, the bottom plate capacitances, the error in capacitor values and many more will have a toll on t
Hello , I want to design First order Switched Capacitor 1-bit Sigma Delta ADC. I want to use an OTA and comparator. The A/D converter must provide at least 50dB snr (signal tonoise ratio) over a 100kHz signal bandwidth. Minimum sampling frequency: 64 MHz ,Differential Input range: 1Vppd , Power dissipation: less than 30mW Can any
only difference in dc, snr is same.
i have seen that someone use inverter with built-in threshold as comparator ,but havent seen latch comparator with built-in threshold, does your flash adc with two stage opamp design work well ? how about its inl dal snr and so on?
Is there anybody who can tell me how to determine the minimum gain in two order sigma delta ADC. I also want to know the answer of this topic. Below is my thought : In nyquist rate comparator said, if snr required is 80dB, the minimal quantization noise is 1/10000 V= 0.1mV (if the signal is 1V). then ur comparato