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23 Threads found on edaboard.com: Soc Design Project
Hello all, I am working on a project where I have to design the PCB. I have designed the PCB similar to the CC2541 sensor tag... I have used cc2541 soc, temp sensor TMP102, DC-DC convertor and a soc debug flash...I have completed the designing part and now I am working on the code.... (...)
Respected and Dear All, Please let me know all the private institutes in hyderabad which trains and guides the final year students in completion of the project work of M.E level (VLSI design and Embedded Systems) . I'm interested to learn RTL to GDS2 flow for a complete ASIC design viz soc design (...)
Power is one of the biggest challenge in sub-nanometer designs. So any thing on low power will be good.
Hi guys, I am a digital design engineer with 3 years experience. While working with analog engineers for soc project, I found that Analog design is very interesting. So, I started thinking about changing my career into Mixed-signal engineer, but I don't know where to start. Already I have read some of analog books and (...)
Hi guys, I am a digital design engineer with 3 years experience. While working with analog engineers for soc project, I found that Analog design is very interesting. So, I started thinking about changing my career into Mixed-signal engineer, but I don't know where to start. Already I have read some of analog books and (...)
Hello, I am doing a project on designing a soc using RTL to GDSII encounter v9.1. I am new to this stuff, hence I am planning to start with an 8 bit microsystem. Could you help me to start with? I was wondering if there is any possibility of getting verilog and LEF files for the MCU so that i could directly import the (...)
Hi all, My name Tri. I am studying soc subject and I have a senior project. It name "design simple processor". I just wrote RTL coding, simulated functions and built gate-level netlist using Buildgate tool. It run well and I have the netlist. According to design flow, The next step is netlist simulation with Modeling (...)
Hi everyone, I doing a mini project for soc. I am designing a vechicle speed controller using Verilog and synthesis using Leonardo Spectrum. Then, the schematic is generated to layout by using design Architect. During my progress in ic station, i create a new cell for the layout and using schematic sdl file. Then i use (...)
As an soc design engneer, we often focus on rtl design, verifcation, dft and sta... But do you want to be a soc project manager? And how to do that? We should know risk control, resource management ,time control and .... Can you give your tips ?
I work for a consultancy company in India, and as a hobby I make project on topics like FPGA, Embedded Systems, soc and full custom chips. If any body is interested, can contact me.
Hi all, I am working on a project using Cadence First Encounter 4.1 and I want to add some test pads or probe pads to the design (not I/O pads) and my question is: Should these pads be a part of the cell library ? because the library documents did not mention any thing about probe pads, OR shall I edit some wires to get the d
Hi ASIC & soc designers, I need a clarity on complete spec to final silicon to customers :- Please comment 1.) First any company will qualify the project / economic and benefit of doing and all. 2.) Customer Specs and Customer design 3.) CPU design and DSP core design 4.) (...)
Hi guys Its my final year graduation project I decided to design a mixed-signal soc I thought about a big design,like a single wimax chip "baseband + RF" but lot of my friends told me that the RF part of this design will be very very hard and complex, specially for me because I dont have any (...)
I want to choose a subject for my final term project or proposal... I'm studying electronic in a BSc course but other EE topics is also fine. I prefer a topic that have these feature. 1.I want to use and actually make some experience in soc design. 2.I prefer a topic that be challengeable enough or have capability for writing an (...)
hello, I'm starting a project about a 2D hardware accelerator design, which is a sub-module of a soc chip. The chip's target application would be Portable Media or Mapping applications, and my graphics 2D module need to support some drawing features like line, circle, etc.. I'm planning the detailed specification. can anyone give me (...)
hi I m sandeep planning to do project in semi-custom VLSI design either in Front-end using Encounter RTL Complier Cadence synthesis tool or in backend using soc Encounter Cadence Place n Route tool. plz help if anybody have projects on this
hi everyone! We will start a soc project, using MTCMOS methodology, I dont know how to start ? it seems difficult to find mature design examples, and the design flow/methodology is not very clear to me. I want to be ready before the project start, can you give some advice ?
Hello, I am working on an soc with ARM. project uses AMBA AHB bus. I have understood the AHB protocol. The testbench is written for complete soc by writing code for ARM processor. I would like to know if there is any book on soc design, verification, etc Aspire
Our project is a 100M soc , and process is 0.18, and how much timing margin should leave? thanks.
Hi everyone We are just starting the soc design project which includes large digital logics & PMU(DC-DC converter) & Audio CODEC (or D-Class AMP) We are concerned about noise/interference/EMI issues when all these block are integrated in single chip. (especially about grounding, shielding, de-coupling, etc) is there any (...)