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88 Threads found on edaboard.com: Soc Layout
How to calculate the delay after layout generation( post layout) in combinational circuit multiplier design in cadence soc encounter. How to give clock in timing constriant file in combinational circuit design . I want to see area, power, delay after layout ram dear lord, you are lost. you give a clock constraint
Hello All, I designed a layout in soc Encounter using NangateOpenCellLibrary 45nm which had zero geometry and connectivity violations. I then exported GDS file and verilog netlist from Encounter. I went to Calibre to run LVS and afterwards PEX for post-layout simulations. Here are my steps: 1) run v2lvs command "v2lvs -v (...)
Hello All, I designed a layout in soc Encounter using NangateOpenCellLibrary 45nm which had zero geometry and connectivity violations. I then exported GDS file and verilog netlist from Encounter. I went to Calibre to run LVS and afterwards PEX for post-layout simulations. Here are my steps: 1) run v2lvs command "v2lvs -v (...)
I have a designed a layout in soc encounter based on NangateOpenCellLibrary 45nm. I want to modify the minimum spacing between only two wires of Metal4 to be from 0.14um to 0.07um, so I modified the minimum spacing of Metal 4 layer in LEF tech. file of the used library. If I want to do RC extraction after this modification, should I also modify min
I tried importing my layout (was generated in soc encounter) in Virtuoso using DEF file and I attached the std cell library and tech. file. The imported layout in Virtuoso have the same std cells and routing but the layers have something wrong. When I first imported DEF file, I had these errors in the attached photo 136594[/AT
I'm trying to open my GDS layout in Virtuoso after exporting it from soc encounter. In the export I merged the GDS files of all std cells as well as the map file. When I streamIn in Virtuoso, I attach the std cell library which was used in encounter. Then I get the complete design in virtuoso but in drawing with no metal fill at all and I ge
Thanks for your reply When a draw an extra wire, it is assigned to the net next to it. I want to a assign a new net for it (which is not included in the netlist) so in order to be able to measure the crosstalk between two different nets. My layout is an AES encryption core of 27332 gates. So what is the best RC extracti
I have a layout design in soc encounter to which I want to add manually some extra wires to the layout (these are EXTRA and don't have anything to do with the design netlist) and modify the gap between another some wires (to measure coupling capacitance and crosstalk effects between wires). I'm using NanGate 45nm Open Cell Library. I'm (...)
Hello, I have a layout design in soc encounter to which I want to add manually some extra wires to the layout (these are EXTRA and don't have anything to do with the design netlist) and modify the gap between another some wires (to measure coupling capacitance and crosstalk effects between wires). I'm using NanGate 45nm Open Cell (...)
2.5) For huge soc designs there is something called HAL checks. I know that VCS and Cadence, HAL can be enabled during RTL compilation. 5.5) Depending on how much RTL modifications were done after the synthesis-engineer had proceeded with synth. the design, LEC can come in here. 6) This is not always necessary. Post layout simulation would be n
Hi All Is there any special commands for fixing Setup and Hold violations after post Route. thanks You have to deal with them separately. The standard practice in ASIC/soc designing is to fix all setup violations before the PnR stage and let the layout engineers fix the hold violations during the PnR stag
Dear all, How can i import cell delay from an SDF file into Hspice? For a specific project, i should create layout for my designs to obtain accurate delay models. I use soc Encounter to create the layouts and obtain cell delays using generated SDF file. Now, i want to model my circuits with Hspice but with cell delays using generated SDF. (...)
Dear all, I hope this is the right place to ask for your opinion. I'm designing a mixed signal ASIC and I'm wondering which could be the best design flow for my case. I'm new to mixed signal but I've already taped out a few analog chips and I can manage to synthetize and layout (with soc encounter) small digital blocks. My Chip has onl
Why it is important to verify soc initialization sequence using SDF annotated post layout netlist ?
Hi, I have specific pair of cell instances in my design that should not be placed very close to each other? Is there any way to specify the spacing between specific cells?
Hi everybody I have a placed and routed design in soc Encounter. I want to feed some test vectors to my design and extract its logical outputs. Since the logical values of primary outputs in my design are dependent on the exact delay of paths, i had to place and route my design to account for the net delays and other parasitic factors. Now the que
hi i want to plot the IDDQ of a simple design. i have two ways help me to choose one. hear are the ways 1. make a layout using soc encounter and convert it to spice model using calibre 2. synthesize the design using design compiler and using command v2s to extract the spice model help me plz
Hi All, Is there any way to force a specific cell gate to be placed (not to be placed) in a user-given region of the layout (using soc encounter?) thanks V.
Hi, I need to compute the post-layout power consumption in soc Encounter, however, for creating power grid libraries it requires an ICECAPs technology file. I am using TSMC 65 nm general purpose standard cell library. Does any one have some experience in dynamic power analysis with soc Encounter to help me in this issue? Regards, Mojtaba
Looks tome like your LEF library doesn't match your timing library or your Verilog netlist Does anybody know Synopsys Design Vision library and soc Encounter lef files which match together?