Search Engine www.edaboard.com

Soft Macro

Add Question

14 Threads found on edaboard.com: Soft Macro
You need to tell us more. 'memory' is not 'hard macro' unless you mean in specific hardware instances or a software macro referring to fixed memory addresses. Brian.
I would call them soft Ip's and not macro's.. no these are technology independent cells The soft IP/DW will map to the technology you are using or intend to map to
can u give me clear diffinition of soft macro? 1.Why we r using soft macro 2.Wat is the advantage 3.Wat cenario will we use this.. 4.wat diff b\w softmacro and std cell... 5.Normally macro's will be in the netlist or not..
A macro is an IP you buy/download. A module is RTL code you write yourself or other people in your company write As for soft vs. hard + definitions check here
Hello All, What is the difference between hard|soft macro, partition block and black box. Also, when we talk about the placement status of a block, what is the difference between placed and fixed? Also, what is 'cover' in the same context? I understand that 'unplaced' will allow the macro to be auto placed by the auto placement (...)
soft IP is when the IP vendor supply you with an HDL model of the IP along with SDC for constraining the IP during synthesis. Hard IP is when the vendor supply you with a physical model of the IP for physical implementation along with a timing model for STA, and a verilog or vhdl model for simulation. In both cases you must hand instantiate the I
Hi friend, Pl check this link Thanks, Sowmya
Halo is a soft constraint whereas blockage is hard constraint. For example, we can use halo around any sub-block or macro. In that case, the tool will try to refrain routing in those area but still the pins of the macro will be connected using routing. For blockage, the tool should not route even the connectivity to the pins. However, tools (...)
A "soft macro" is a sub-unit of a chip (eg: a USB controller) that is presented as RTL code. Synthesis, placement and routing have not been done. A "hard macro" is a sub-unit of a chip that has been synthesized, placed and routed so that the designer gets it as a GDSII layout description. A soft macro (...)
Hard macros are fully placed/routed macros that are available as post P&R netlists. These netlists cannot be modified and can be placed directly into the final chip design. soft macros come in various forms such as RTL code, synthesized netlists,etc. These macros can be modified.
in JupiterXT, soft macro will cause the original hierarchy changed. I used to use Astro, which can detect scan chain and can route it in last. Maybe JupiterXT has the same functions. In my opinion, you can just load you scan-inserted netlist, extract softmacro, and automatically detect the scan chain in (...)
in HFSS, you should use scripts not macro and you can run it directly in HFSS 10 without anz other soft
soft macro: - RTL source code in Verilog/VHDL which can be synthesized into different technology libraries. - Example: ARM7TDMI source code - Can be targeted into user-defined process technology, such as TSMC 0.18um or UMC 0.13um, .... - Provided in VHDL(.vhd) or Verilog(.v) format ------------------------------------------------
soft macro --> RTL IP. Firm macro --> Netlist targeted for any process. (can be for Fpga or ASIC) Hard macro.--> GDSII Layout of the design.