Search Engine **www.edaboard.com**

16 Threads found on edaboard.com: **Spectre Snr**

hiiiiiiii
I'm working on sigma Delta ADC
CAN ANY1 PLEASE HELP ME ON WORKING WITH CADENCE **spectre** FOR **snr** CALCULATION
TRANSIENT ANALYSIS DON E WITH
FIN=50HZ (OSR=64) (SINE WAVE)
FS=12800HZ=CLK FREQUENCY
HOW MANY CYCLES I SHOULD RUN THIS TRANSIENT ANALYSIS??
wats d funda of skipstart,skipstop, strobeperiod
& HOW TO CHOOSE
STROBEP

Analog Circuit Design :: 02-05-2011 19:11 :: kapil411 :: Replies: **10** :: Views: **4802**

hiiiiiiii
I'm working on sigma Delta ADC
CAN ANY1 PLEASE HELP ME ON WORKING WITH CADENCE **spectre** FOR **snr** CALCULATION
HOW MANY CYCLES I SHOULD RUN THE TRANSIENT ANALYSIS??
IN ORDER TO CALCULATE **snr**
PLEASE HELP ME IN FIGURING OUT THESE VALUES...
how to come to conclusion to FFT fundamental frequency of input signal ,
NO. (...)

Analog Circuit Design :: 02-07-2011 17:06 :: kapil411 :: Replies: **3** :: Views: **4752**

Hello friends,
I'm working on a second order switched capacitors sigma-delta modulator,
I want to calculate the **snr** of the modulated signal (output of the modulator),
Please can anyone help me how to calculate the **snr** of this signal with the calculator of CADENCE,
Thanks in advance.

Analog Circuit Design :: 09-03-2008 11:50 :: Firas :: Replies: **7** :: Views: **6916**

Hello,
I am using Cadence **spectre** and how do I calculate **snr** for ADC? Is there any direct step to do that?
Thank you.

Analog Circuit Design :: 07-22-2009 22:56 :: praveen426 :: Replies: **0** :: Views: **1285**

I use Diff-opamp with low rout ( while not OTA ) in **spectre** (using verilog-A) to construct the sample-hold amplifier for ideal pipeline ADC simulation, But I found that with this low rout Opamp, I had to set large opamp gain and GBW to obtain the desired **snr**/sndr. That is to say, when the gain and GBW is set to the value suitable for a certain ADC

Analog Circuit Design :: 04-29-2009 05:55 :: iamxo :: Replies: **0** :: Views: **1630**

maybe the fft algorithms are different. I always output data from **spectre** and fft them with the same fft algorithm as in simulink.

Analog Circuit Design :: 08-27-2008 06:12 :: turtleden :: Replies: **3** :: Views: **1821**

Do the FFT (either hspice or **spectre**),we get the spectrum of the signal.
From the fig,we can only get the SFDR,how can I get the **snr**?
Cheers!

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-04-2008 05:54 :: pikky :: Replies: **0** :: Views: **912**

Hello,
Please any one help me how to find **snr** in **spectre**.
Bye

Analog Circuit Design :: 04-20-2008 11:03 :: amahi07 :: Replies: **0** :: Views: **1129**

hi, guys
how to simulate ADC's **snr**, THD, SNDR in **spectre** or hspice ?
if before S/H, there is a buffer, which spec of the buffer is important, THD or HD3?
is the THD of the buffer well below 6.02*N+1.76 dB?
thank you very much!

Analog Circuit Design :: 06-05-2007 19:27 :: qqic :: Replies: **1** :: Views: **2483**

hi can anyone give me some reference books or examples?
thanks

Analog Circuit Design :: 04-10-2007 00:25 :: zxasqw123 :: Replies: **0** :: Views: **1824**

You are basically making a mistake here. The main noise contribution comes from the quantization noise which is at about 60 MHz. Some extra noise is aded due to device non-liniarities etc.... By sampling with Nyquist Criterion or nearly to that, you are not allowing the noise flour to appear in your calculations. To see your noise flour to some bet

Analog Circuit Design :: 03-07-2007 11:01 :: gunturikishore :: Replies: **14** :: Views: **14667**

The SNDR can be calculated by the calculator in **spectre**RF. For the **snr**, you need to exclude the distortion products shown in the spectrum. Remember, it is not the distance from signal peak to noise floor -- this distance is usually called SFDR (spurious free dynamic range). Only knowing the noise floor is not sufficient, you also need to know how m

Analog Circuit Design :: 04-09-2006 17:56 :: willyboy19 :: Replies: **12** :: Views: **21631**

The input bandwidth of the ADC is the input frequency at which the SNDR is 3dB below the maximun value, and how can i simulate in **spectre**? Thanks.

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-15-2006 13:24 :: wan :: Replies: **1** :: Views: **1214**

Good guys:
I have a question about the simulation on ADC'S ENOB with cadence **spectre**. How can I simulate the bit number of a pipelined ADC in **spectre**?
Thanks.

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-23-2005 07:18 :: wan :: Replies: **1** :: Views: **1541**

for **snr**, you can use **spectre**
.pac
.pnoise
and for high order(>2), should pay attention to the stability, so the out band noise gain most less the 2.5 or so.

Analog Circuit Design :: 11-28-2005 01:34 :: sunking :: Replies: **3** :: Views: **1406**

Quote:
Analog_starter
Hi, how can I do **snr** simulation by Hspice ??
BTW, in **spectre** can I add .vec file into it ??
Using .fft in hspice can do fft simulation and get THD. And .vec file can be used too.
But for **snr**, i don't kown how to simulate it.

Analog Circuit Design :: 05-11-2005 06:04 :: derekqiao :: Replies: **10** :: Views: **2816**

Previous
1
Next

Last searching phrases:

fpga mac | lcd spartan | filter noisy output | antena theory | electromagnetics | interpolating adc | plc gsm | hfss start | google ads | esd vcc

fpga mac | lcd spartan | filter noisy output | antena theory | electromagnetics | interpolating adc | plc gsm | hfss start | google ads | esd vcc