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55 Threads found on edaboard.com: Spectre Veriloga
Hi, I'm new to Verilog-A I am having convergence issues with a device I modeled in Verilog-A. When I have the device simulated in parallel with a time varying voltage source then the simulation seems to work okay. The issues arise when I try to simulate transient behaviour of my device in series with an added resistor and the voltage source in p
Cadence spectre can not accept Verilog-D. You have to use NCSim with AMS option which is called as AMS Designer. Or legacy VerMix(=spectreverilog) which is a cosimulation between spectre and Verilog-XL might be available.
Hello, I was trying to use veriloga to write a model file and simulate it in Virtuoso Cadence. When I try to simulate i get following error Missing or corrupt .oa file in cellview 'memristordesign/memristor/spectre cmos_sch cmos.sch schematic veriloga'. The OSS netlister can only process cellviews that have a valid .oa file. This file (...)
Hi all, I am trying to run monte carlo analysis on a variable, from veriloga model. I had initially done the implementation with cadence-spectre flow. below is the example of how it is achieved in cadence-spectre. I put it here, so i can explain clearly what I want. 1. included the following in veriloga (...)
I think this is best done in veriloga (which spectre digests just fine, and Cadence supports editing and view-switching). You will want to error-trap that denominator, and a poly- source / analogLib primitives kludge probably doesn't have much for that. I'd recommend to find a resistor veriloga model, off the Web, and just mess with the guts.
Hi, I tried to build a veriloga VCO phase-domain model by referring to Ken Kunder's paper. Then I have no idea how to start with, thus I set up a simple testbench as below image shown. I chose "noise" analysis and run. spectre then showed error indicating "Matrix is singular (detected at 'I0:idt0'). When I tried to remove below codes and re-
If I understand you correctly, you are just not seeing simulation results for the "ncnfet" terminals? I think I ran into that many years ago, and found I needed to put some more traditional analog element in series with the veriloga output (like a trivial 'res') to force the veriloga<->spectre interface to bring out the node data (...)
Hi all, I design 3bit idea DAC using veriloga to decode the signed binary to decimal. My purpose is change: 100 -> 4 011 -> 3 010 -> 2 001 -> 1 000 -> 0 111 -> -1 110 -> -2 101 -> -1 I used modelwriter tools in Cadence spectre to design DAC with parameter (max voltage = 4; min voltage = -3, threshold = 1). However, its result is wro
Hello everyone, I am trying to write a 2x1 multiplexer using the mems switch in veriloga. But when i try to simulate the circuit i am getting errors. ERROR (spectre-11005): Matrix is singular (detected at `out'). ERROR (spectre-16080): No DC solution found (no convergence). Here is my code. `include "disciplines.vams" `include
You can do almost anything you can conceive, in veriloga and spectre will digest it just fine; you have to create the veriloga view alongside the symbol and make sure that it is picked up by your switch / stop view list order (or by using Hierarchy Editor and config-view based simulation).
I am trying to do a mixed signal simulation with AMS under cadence\virtuoso. this is for an old testbench which was working fine with spectre simulator, but then I replace a logic block with a verilog code instead of an old one with veriloga (then I need AMS). the new Verilog block has no problem, as I am able to simulate it in a separate tes
AFAIR SPICE & spectre don't support variables in VPWLF files. Use a math tool (Excel, Matlab, ...) to evaluate the variables first, then use the CSV format to transfer the values.
I would recommend, then, that you try and dig up a veriloga version of a standard FET model (like, try Silvaco's web site) which will be somewhat human- readable and let you edit equations as you see fit. Then you need a version of SPICE, spectre, whatever that supports veriloga code blocks.
What simulator do you use ? Try few simulators, such as HSPICE, XA, spectre, eldo, ADSsim, GoldenGate, etc.... As far as my experience, I often encounter bug in HSPICE Verilog-A compiler.
When i'm running spectre simulator to simulates a circuit's behavioral model by verilog-a, this problem has occured. Any ideas?
Hello guys, I was given a component in a format (compiled veriloga is my guess) and i would like to make it a cell in virtuoso to include it in a schematic and simulate it with spectre. Do you guys know how to do that ? One told me to create a veriloga cellview then include this symbol in my schematic and then to replace the of the
hello guys, i am tryong to generate a counter which has a 10*clock period, by doing a simple verilog A code, on cadence ,spectre simulatior, but the issue is that the simulation takes sooo long time,( +20 minutes ), so is this normal? my code is : // veriloga for lte, counter, veriloga `include "constants.vams" `include (...)
Hi, I meet a problem of convergence when I use veriloga to model the SH circuit. I first use veriloga to build the model of capacitor, ideal switch and ideal opamp, but when I do the simulation with spectre, It tell me no convergence, how can I do with this problem? thx!!
Hi all I am running cadence spectre veriloga simulation using ic610 and mmsim10.1. The output shows ERROR (VACOMP-1008): cannot compile ahdlcmi module library spectre. My OS is ubuntu 11.10. Anyone can help me to solve this problem? Thanks alot Best Regards Tom
Hello, I was trying to use veriloga to write a model file and simulate it in Virtuoso Cadence. When I try to simulate i get following error Missing or corrupt .oa file in cellview 'memristordesign/memristor/spectre cmos_sch cmos.sch schematic veriloga'. The OSS netlister can only process cellviews that have a valid .oa file. This file (...)