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Hi, Isn't a 1 bit DAC just a (analog) switch? In simplest case just a transistor? With an analog switch you are able to generate three states. Specifications: * switching speed * ON resistance * charge insertion ... Klaus
I hope that you are asking for the speed of the ADC conversion. It may vary with type of ADC.
Hi daer all; I have a question that for an 8-bit ADC for low-speed industrial applications what is the accepted minimum ENOB for interested bandwidth? I designed and implemented my sigma-delta ADC on FPGA; but the ENOB for lower frequencies (20hz) starts from 6.4 and for highest frequency in the bandwidth (8khz) is 4.9 are these values
In Continuous Time delta sigma ADC, there are two options in Feedback DAC generally. (1) Current DAC (2) Voltage DAC or Resistive DAC Regarding thermal and flicker noise, (2) have advantage. Regarding calibration for multi level DAC, (1) have advantage. Regarding speed, (1) have advantage. (1) occupy large area than (2) (...)
I need help regarding a 5th Order sigma delta ADC design .. CLK = 384 Mega Hz ... what is the most suitable type of to implement the feedback DAC ? as i already tried the most simple structure and it's not working good with this high speed CLK ... i read about 'current steering DAC ' for example , is it suitable and accurate enough for (...)
To choose the architecture, it's all about trade-off. There is no "best" architecture. OSR - filter order - number of bit for the quantizer - continous time vs switched-cap... Each architecture has advantanges and drawbacks. It depends what you expect from you design : high accuracy ? high-speed ? low-power ?
I'm working on the sigma delta modulator, and I would like to extract the dynamic Performances like SNR, SNDR, SFDR.... I would like adapt maxim program for Dynamic Testing of High-speed ADCs to my work,(Selecting the Optimum Test Tones and Test Equipment for Successful High-speed ADC Sin
Maybe you do without the switching elements. But this depends on the accuracy and conversion speed you need. Consider a fixed 5000 on 1 voltage divider, and a 24bit sigma-delta ADC, with a full scale for 1Volt (as example). This means that the lowest range (0 - 5V) becomes (0 - 1mV) and you still have a resolution of (2^24)*1e-3 = (...)
Why sigma-delta A/D converters are mainly dedicated to high-speed applications which can tolerate offset and gain errors? Thanks!
hi sandhaajith, the offset and hysteresis requirements of the comparator in sigma-delta modulator is relaxed and the high-speed is required, so it can be designed with a preamplifier followed by a latch with reset. see this paper: ?A High-speed CMOS Comparator with 8-b Resolution,? IEEE J. of Sold-State Circuits (...)
why the sigma delta adc is so slow. means why we can not use sigma delta adc for Mhz speed
Schoofs R., Steyaert M., Sansen W., "Analysis of Gm G and RC filters for high-speed continuous time sigma-delta A/D conversion", in proceedings of International Symposium on Signals, Systems, and Electronics, Linz, Austria, August, 2004 Thanks
Audio:High resolution low speed->delta sigma ADC Video:High speed median resolution->Pipeline ADC
well in analog may be PLL or high speed data converters on FPGA DSP
there are some books and thesis they are good, i think book Top Down Design of High Performance sigma delta Modulators-Medeiro-1999 DeIta-sigma Data Converters-Norsworthy Understanding delta-sigma Data Converters(Temes) thesis High-speed, Low-Power (...)
hi all, i have a question about sigma-delta modulator architecture selection. someone tell me that using cascaded modulator when designing low osr and wideband, using single-loop modulator when designing high resolution and low-speed. this is right? thanks advanced!
search the following: continuous-time delta-sigma modulators for high-speed a/d conversion: theory, practice and fundamental performance limits by james A. cherry one of the very first books discussing ct dsm and many theories and issues were firstly discussed and studied in this book; actually u only need to download cherry's transanctio
what is the speed and resolution of ur sigma delta adc. regrds
To achieve 6bit/560M character, my suggestion is to select pipeline structure, since your design is neigher high-speed(flash is suggested) nor high resolution(sigma delta is suggested). Best regards, hi i need to design the ADC for UWB transreceiver... the spec of adc is 6 bit resolution and the speed is 560 msps.. (...)
Hey try and design using an integrating architecture. I would suggest a dual slope or a quad slope architecture in order to achieve the required resolution. There are designs using integrating architecture and achieving a 16 bit resolution. Only you should be able to achieve that speed and good component matching. And importantly, the speed is a cr