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36 Threads found on edaboard.com: Sram Library
Hi all, I have been out of ASIC design for sometime now. Just want to check if using a cell library would the cell library also provide the ability to initialize small RAM modules ? , Say 128 byes or so. I am wondering if this is going to be sram based with simple access interface, could you provide the interface signals Also just (...)
hello. I want to know how to calculate snm for complete architecture??? and then for sram array?
Hi all, Can any one help me to develop a code for sram in hspice by using FinFET technology,I have BSIM CMG and IMG models but don't know how to develop code.Can any one guide me about this. Thanks all in advance
Dear scholars I need the 15nm FinFET technology file to simulate a conventional 6T sram. Would you mind providing me with this file? Many Thanks in advance
I need library files for the jpeg image in verilog for read an image from the sram memory
Hi, I am working on designing an sram that would used as part of a processor. Once the schematic and layout are done, I need to create a timing library for the sram module. I need the liberty for further use by tools like Design Compiler, Encounter, Primetime etc. However, I am not sure of what tool can be used for creating the timing (...)
Hi, I am going to integrate a Motorola MPC555 in my design alongside other parts such as sram and EEPROM. Has anybody designed a board containing a Motorola MPC555? Or, is there any library which can help me in this case? Thanks in advance,
I have an sram memory . it's data width , address bus width and depth all are sram depth is d and the address bus width must be log2(d) and represented by c parameter . I import the math function library by several methodes in my code but neither of them worked and there were errors. I don't know how to write the width of address b
I want to build a simple memory module in design compiler How can I write the VHDL or Verilog code in order for the compiler to build the module using sram cells ? Is there a tutorial or an open source code for a memory module than can be compiled to produce an actual design with sram cells ? I have TSMC 0.18 um library files
Hi, I have been working with Arduino UNO for my projects , it worked fine for me.But my next project requires more RAM (atleast 1 MB) as it has more data usage . UNO or other arduino wont work as it as less sram . Can you please suggest me other microcontrollers which have a easy to use library as arduino provides ?
It's like I compile some C funtion to my library, send it to target (via usb), who will update/substitute DSP processing function to the new one saving in into the sram. C language recognise function as an address of its beginning, right? I would implement like two sram spaces for two functions I will switch between them ev
I need to design a system using sram or register file, but i have no experience before. Do i have to code it in vhdl or using some tools to generate sram. I notice in website of synopsys there are many IPs for sram or register file, how can i use them? thanks~
Logic library (for example, it is synopsys liberty file or synopsys library) contains timing, power, noise, logic (sometimes) info about cells. If the cell is complicated enough (like sram), this library may not contains logic (behavioral) description. Physical library (for example Synopsys milkyway (...)
Hello everyone, I need your help! Thank you in advance. Does anyone know the approximate value for the pull up PMOS, the Pull down NMOS driver, and access NMOS transistor for 40nm or 32nm sram cell? I just need a approximate value for reference. We want to do a hspice simulation for a sram cell using PTM 32nm library. But we don't (...)
hi i want to read and write to sram from fpga with variable address , but its stuck always :sad: here is the code , if there is any mistake plz tell me library ieee; use ieee. std_logic_1164.all ; use ieee.numeric_std.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sram_ctrl is port ( clk, reset: in (...)
Dear All, I need to estimate the power of my designed circuit in Synopsys power compiler(of design compiler). I have .db file(library) for TSMC 0.18um Technology, but it doesn't include sram , and it recognize all of my sramS(about 3Kbit) block as DFF, which cause a lot of extra power consumption. I am looking for another (...)
I recently picked up a book from the library, 'Programming Embedded Systems in C and C++', for learning embedded programming. The code in the book is based on an evaluation board with the following specs: Processor: Intel 80188EB (25 MHz) RAM: 128K of sram (256K available), with optional battery backup ROM: 128K of EPROM and 128K of Flash (512
I have the library files of tsmc 90nm sram module. In the library I found the .db file and two .v files. One of the .v file is on RTL level. So I assume if I use the RTL module in my design and include the .db file in my link_library when I synthesize it in dc_shell, I should be able to get synthesized sram (...)
It is spice3 code, based on berkeley transistor model for 35nm structure. See: sram MODULE how it works ? Rosa
Thank you!! I didn't include .v file from my sram compiler but do include .db file. Design compiler consider my sram as a black box, so there is no sram synthesized in my gate level netlist, but timing report contains sram timing information. This is exactly what I want. %dc_shell> check_design to check there are an