Search Engine www.edaboard.com

Sram Low Power

Add Question

18 Threads found on edaboard.com: Sram Low Power
Hi, My friend told me, he designs an ultra low power sram, 28nm process operate at 2GHz, active current only 2mA. The memory size is 8k bytes. Operating power is 1.0 V. Is it possible? In my memory, the current is over 20mA in exist memory technology. It seems impossible. Anyone give opinion?
Be a postgraduate student, I study on the design of sub-threshold sram now. The papers I have been collecting are all emphasize how to increase the stable of sram Cell. Such as write noise margin、read noise margin and so on. However, there are no references show how these periphery circuits (ex. column decoder, read buffer??and so on.) are d
Does anybody know a serial (SPI, I2C) 32KByte sram supporting 2V - 3.6V voltage supplies? 23A256 is the closest solution I found but Vcc can go only up to 1.95V. Thanks!
Hi everybody, I am puzzled with the cache decay (ISCA01, Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage power) and DRG cache (DAC02- DRG-Cache: A Data Retention Gated Ground Cache for low power). The former said that the gated ground sram lost data, while the latter said the gated-ground (...)
Hi, Have not used that micro, but a quick look at the datasheet details standby voltage and current for sram, controlled by the standby pin, so looks like the circuitry for low power RAM standby is already there for you to use. Apart from that, is probably wise to store all your key ram values in eeprom so if all power is (...)
Hi all... I am in a process of designing a low power sram memory array.For that i have designed a single bitline architecture sram cell which consumes less power.Now i have to extend the memory to 256kB (512X512) memory of 4 bit bit a part of this i have to model the bitline and wordline in terms of the (...)
Hi all... I am in a process of designing a low power sram memory array.For that i have designed a single bitline architecture sram cell which consumes less power.Now i have to extend the memory to 256kB (512X512) memory of 4 bit bit a part of this i have to model the bitline and wordline in (...)
Dear Friends, I have a project work on "Various techniques (Circuit topologies, Process and matterial parameter combinations) for low power memory cell design" but I can't understand what are different circuit topologies and what does process and matterial combination mena for sram. Please clear my doubt. Thanks and regards Satish Kumar
What's the best sram configuration? (4T, 5T, 6T, etc). I am designing an sram with low power and low leakage in digital implementation using Verilog coding (VCS simulation). Also, what's the best technique I can use to minimize the leakage? Thank You!
I am designing an sram for my special project. I want to make a breakthrough (like Ultra low-voltage, High stability, low power, etc), but what should I consider in order to get these breakthroughs? What would be a great design? What breakthrough should I design? Thanks!!!
Hi Does anyone know about the issues of "Subthreshold sram Design"?
Following Table shows that sram power dissipation in writing and Reading operation. ( It's from "A low power sram USing Hierarchical Bit Line And Local Sense Amplifiers, IEEE, 2005" ) The sram consumed 28mW at Write operation. Question : What is "Write operation" (...)
could somebody explain how to use scan chain and sram for retention
low power memory design is a very advanced varies depedning on what type of memory you want to it sram or EPROM or DRAM?? low power involves proper frequency of operation.Efficient recharge cycle and Controlling various variations (Charge and discharge)happening across the bitlines. There are several (...)
has anyone implemented the PHY itself as software ? It's a chalenge for you at 2.4 GHz. Why don't you try what is already done in the market ? You have an 2.4 Ghz IEEE 802.15.4 compliant RF transceiver and 32 MHz syngle-cycle low power 8051 MCU with 128 kByte in-system programable flash and 8 kByte sram in a single
Hi, it's possible to connect a sram or DRAM to a 16F877 for example, but try a non egzotic RAM like: W24512AK-15 64K*8 bits high speed, low power CMOS static RAM from Winbond good luck, Zed
some material about Psram Interfacing Toshiba Pseudo-Static RAM with Toshiba MIPS RISC and Motorola powerPCTM Processors: Including a performance comparison between Toshiba Pseudo-Static RAM and low-power sram
hi,try: they have all kinds of high speed low power srams. some chip from IDT is ok,too: hope can be helpful.