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94 Threads found on Sta Help
Hello everyone I am working in a small personal project which is a poor man's soldering station, or so. I have made the complete diagram, the solder iron and hot air gun connection and sensors positioning, the 1st order (proportional) temperature controller with PWM output which will activate an opto diac, connected to a triac and the heaating e
I guess this link will help you understand better.
After synthesis, you can check: - Clock ideal sta. Knowing critical parts about timing in you design functional mode. - Area ( Without clock cells and optimization cell from PnR ). Inform it to PnR members would be helpful for them. - SDC quality. ( report by check timing and so on .. ) If you want, you can check power report, but it is not close
Hi All, I have 2 questions got from an interview. I did not find any answers online and hope you could help. 1. After the timing is fixed in PBA mode, can it be tapeout then? Or it needs some extra step? 2. If using GBA mode to do timing closure, it is pessimistic. Is there any negative impact? Any thoughts are welcome. Thank you very mu
In sta or simulation? create_clock -waveform ...
1)please any body will be able to help to find out sta2080 mp3 decoder circuit/datasheet? 2)please try to help me to design mp3 decoder with atmega micro controllers only without using any extra mp3 decoder chip.
Lockup is between one flop's Q pin to another's SI pin. It doesn't play a role in capture stage.
Hello All, What is the meaning of set_input_delay and set_output_delay? Suppose I have set input delay max is 14 ns and min is 6ns(calculated on basis of setup,hold, min path delay and max path delay). If I set input delay -max 14 -min 6ns, does it mean that data must reach before 14ns? Please help me to understand this. Is there any po
Hi All, Could someone point me to the good slides (or book) of sta training WITH EXAMPLES? Thank you!
Hi I am making a gsm module controlled circuit for a project, I have designed the vast majority of this, its going to be controlling a pressure alarm system (basically turn off/on a water pump and alarm via sms) I have got everything up and running except the sms module part because I was waiting for it to get delivered before I started. Bu
More information in your question will help? Like : Where you want to define the clock. Like PD or sta or simulation?
Hi, If you want to be :- ASIC Design Engineer :- Learn Verilog, Digital Design Concepts, sta, Should have hands on experience with good simulators like NC-Verilog(Cadence), VCS(Synopsis), QuestaSim(Mentor Graphics), ISE/Vivado(Xilinx) etc. Verification Engineer :- Verilog, System Verilog, sta, Experienced in Simulators above, Digital (...)
Used sta tool to do eco fixing, and it will report the cell needed to fix the timing issue. But the first question, are you able to fix the hold after CTS or/and after routing?
Hi, I have a doubt regarding performing timing analysis for an analog module in a design. I am new to sta and I have read in some blogs that sta does not deal with analog blocks. Please help me regarding this on how my approach should be to perform sta on analog blocks. Thanks in advance!
Hello Friends I need an emergency help. I am studying with amplifier design. I have a TI calculator with that I need to calculate lot of equations, those are below. 1. Reflection co-efficient 2. Impedance 3. Gain 4. Radius of stability circle 5. center of stability circle 6. K 7. Delta so on etc I have to waste too (...)
I'm currently using Xilinx Vivado with XDC. It's very powerful for complex design to meet the goal.
PFA. And for more deatil : see the book : sta for nanometer design.
Hi All, Can anyone explain me what are all the modes and corners(kindly name them) that are available in sta and Synthesis?? I want to know their differences both script level and concept level. Any materials or links are also highly appreciated. Thanks in Adv.
Both Primetime and Tetramax are two different tools used for performing two different tasks. Primetime is used for doing sta (static timing analysis). Tetramax is used for test pattern generation. This test pattern will be used for testing ASIC post production in Fab. Little bit of googling would help you know more.
Can someone please help me understand why PLL input clocks and output clocks are treated as asynchronous to each other in static timing analysis ? Should not we say that they are synchronous since the output clock phase of a PLL is always locked with the input clock ?