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7 Threads found on edaboard.com: Stacked Device
I am designing a stacked CMOS power amplifier using st65nm design kit. The device I am using is nsvt25_rf. While designing cs stage maximum Vdd I took was 2.5V. Can someone suggest the Vdd that should be used in cascode configuration (2.5V or 5V?). Is Vds value specified in design kit the maximum Vdd that should to given or maximum Vds across each
CMOS RF switches tend to use stacked devices on SOI to get high power handling and linearity. I would not expect more than about 1.2V nominal DC rating, maybe 1.3-ish DC max. What kind of AC "bonus" you can claim would depend a lot on how the device behaves at the limits - linearity matters, isolation matters, in addition to simple (...)
Hi all, I have a design that need to have an output voltage swing of 20V and the level shifter and the driver need to be fabricated on the same chip. I have come across a lot of high voltage processes which allows the integration of low and high voltage devices on the same chip. I read a paper on high voltage series MOSFET output dri
OK, It(stem) may be stacked because there are many frequency . And must react to each specifically frequency .
Some designers used stacked structure (cascode two transistors) to increase operating voltage.
In a power IC the bandgap and any cascoding is unlikely to be significant in the end, area-wise. It's the power devices' area. The current for a reference and housekeeping analog should not need much device width. stacked MOS diodes and a resistor make a good enough shunt regulator, a pass follower (high voltage capable) makes a (...)
I have using d-pot ds1267 to get variable voltage at its output. i want to use the ic in stacked configuration. micro used is at89c2051. i am getting the result when used without stacked conf, but not with stacked configuration. Plz provide me with the code to use ds1267 in stacked configuration(ASM code)