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118 Threads found on edaboard.com: Standard And Vhdl
I'm guessing the types for a and b should be signed from numeric_std? Yes - any standard signed type will work: integer real and from vhdl 2008 sfixed std_logic_vector (when using numeric_std_signed) bit_vector (when using numeric_bit_signed)
1. WIDTH is a reserved vhdl name (standard attribute) and shouldn't be used for a generic. 2. There's little use of putting a fixed parameter in a generic. You better use a constant. In practice there may be cases where you wanted to write parameterizable code but took a short cut at some point. So it works with the (...)
The resource utilization of a look-up table implemented in logic cells will strongly depend on the actual table data because it undergoes the standard process of logic minimization during synthesis. A look-up table with little resource usage can be implemented in block RAM, provided your FPGA family has it.
SystemC is the standard for SoC exploration and model IP sharing. As the EDA vendors have integrated SystemC with their Verilog/vhdl simulators, the system analysis model can also be used for early verification. Unfortunately, model construction is very tedious in SystemC, can take months for one IP, and (...)
try using ieee.numeric_std rather than std_logic_arith, because std_logic_arith is not a standard vhdl library. Please post the whole code with the problem, rather than an out of context snippet.
Then the problem is you havent compiled the fixed_pkg code into the ieee_proposed library. ieee_proposed is not a standard vhdl library - it was a '93 compatible version of the new code added to vhdl 2008 to allow people to compile designs in software without 2008 compatibility. So you either need to switch to 2008 code : (...)
You'll notice that all vhdl experts suggest to use IEEE standard library numeric_std instead of outdated std_logic_arith and related libraries. If you are however stuck with the legacy libraries for some reason, you have to use the respective type conversion functions, e.g. conv_signed() instead of to_signed(). - - - Upd
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR); from STD_LOGIC_TEXTIO library (overloads STD_TEXTIO library)
There are problems here because you have included both numeric_std and std_logic_arith in your code. They both define signed and unsigned types - causing a conflict that means you cannot see either type without directly using them. The solution is to remove std_logic_arith as it is not a standard vhdl (...)
the textio package only covers std.textio for types defined in std.standard - integer, real, bit_vector etc. std_logic_textio was defined by synopsys (so is not a standard vhdl package) as a way to directly read/write std_logic_vectors without having to first convert to bit_vector or integer or the like, (...)
There is no write function for numeric std. You have a few options: 1. Include the non-standard std_logic_textio package and convert your unsigned to a std_logic_vector before using the write, owrite or hwrite functions 2. Convert the unsigned to an integer or bit_vector 3. Use vhdl 2008. Each package has textio functions (...)
You just confused the coefficient order. Rather than having c(0) = 1 as assumed in the first code, you have actually c(0) = 4. and so on. By the way. Why in 2015 people are still starting vhdl with the non-standard Synopsys library std_logic_unsigned?
Hi guys, I'm implementing a certain packet decoder. The incoming packet is sliced according to certain ranges defined in a standard. I want to define the slice ranges in a package so that my code is readable and generic at the same time. For example if I'm slicing the control_field then I want to write for example frame_length <
HI, Can we design a look-up table without targeting to FPGA , means using standard FETs in cadence. ? I am new to look up table and vhdl. thanks
Unlike Verilog $readmemb(), there's no standard method to import ROM data to design tools. Some tools understand vhdl files for inferred ROM, some can import hex files for vendor ROM macros. Generating a *.VHD file with a constant array is probably the most portable method.
aside from the non-standard coding style, the problem comes because you are using a signal in a for loop. Signals get assigned when a process suspends, not immediatly (like a variable). So in your case every element in the array is compared to 0, and it will find the last element larger than zero, as a signal takes the last value assigned to (...)
Use Design Compiler to synthesize the Verilog RTL into a Verilog gate-level netlist. Then you can import the Verilog netlist into Synopsys Custom Designer, if you have it, and simulate through that. If not, providing you have the transistor levels models for the standard cells, you should be able to simulate with that. You will just need (...)
This is just a standard N tap FIR. First of all, I suggest you bring in all C co-efficients separately, not as a single bus. Second, for N taps, you will probably need a package to create the array types to make the design generic. I dont know why you have declared RAM and ROM types - there is no RAM or ROM in your drawings. They are just (...)
So what is the problem? Can you post the testbench? why cant you just put a sign bit on the front of the unsigned number? the problem here is you're using the non-standard std_logic_signed library, so you cannot do signed and unsigned arithmatic in the same file. You need to use the signed/unsigned types from numeric_std, (...)
This is just the standard, but you havent posted the problem.