241 Threads found on edaboard.com: Standard Ieee
As said in the standard, you can set default value in the entity declaration like
input_data : in std_logic_vector(7 downto 0):= "00000000";
If you left that port (input_data) open, no error will be reported. You do this in the component declaration on the parent design block.
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-07-2017 12:46 :: sherif123 :: Replies: 4 :: Views: 1753
Are there any EDA tools available that support ieee Std 1735?-2014 standard (a.k.a. p1735 v2) IP encryption? Also, how can I encrypt my IP to make them compliant with ieee p1735 v2 standard?
Professional Hardware and Electronics Design :: 12-18-2016 05:08 :: vpopli :: Replies: 1 :: Views: 1474
In most cases (i.e. ignoring special values in the ieee floating point standard such as infinity and NaN), the only difference between a fixed and floating point implementation is that with floating point you will add a little extra stage which locates the most significant set bit (i.e. the most significant '1', assuming unsigned numbers). The loca
Digital Signal Processing :: 10-16-2016 00:02 :: weetabixharry :: Replies: 2 :: Views: 638
try using ieee.numeric_std rather than std_logic_arith, because std_logic_arith is not a standard VHDL library.
Please post the whole code with the problem, rather than an out of context snippet.
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-09-2016 10:51 :: TrickyDicky :: Replies: 15 :: Views: 609
You'll notice that all VHDL experts suggest to use ieee standard library numeric_std instead of outdated std_logic_arith and related libraries.
If you are however stuck with the legacy libraries for some reason, you have to use the respective type conversion functions, e.g. conv_signed() instead of to_signed().
- - - Upd
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-28-2016 15:12 :: FvM :: Replies: 15 :: Views: 839
For IO testing we do boundary scan also known as JTAG(ieee 1149.1 standard). This includes EXTEST which test the I/O's as well as the logic between two blocks.
One more method is to use NAND tree test for IO testing which includes the insertion of NAND tree structure at all IO pads on the chip.Then apply your NAND tree pattern and observe the outpu
ASIC Design Methodologies and Tools (Digital) :: 03-22-2016 08:29 :: shalin mandiwala :: Replies: 1 :: Views: 594
Follow the ieee standard 1241 about ADC measurement methodology. Apply sinusoidal wave to the input and sampling it with numbers of samples≥2^N and make FFT of collected samples to get SINAD. Next calculate ENOB from formula ENOB=(SINAD-1.76)/6.02
Of course the sampling frequency cannot be an integral multiplicity of input signal frequency to
RF, Microwave, Antennas and Optics :: 02-28-2016 12:29 :: Dominik Przyborowski :: Replies: 3 :: Views: 1100
Hi people How are you All ,
I hope you are all fine ,
I think It will be helpful for beginners like me if any/some of the Experienced members make a Complete Comprehensive tutorial that will pinned about the following points related to each of the international standard organizations involved in Telecommunication Study and Industry :
Professional Hardware and Electronics Design :: 01-05-2016 22:20 :: eng_boody :: Replies: 2 :: Views: 825
Tricky question because if you use some conceptual design as shown it is not real design, then all you can use are block diagrams.
Then you must dream up your own logic symbols using standard shapes and text.
Not very good for detail oriented Engineers but perhaps ok for your purposes.
For example the Johnson counter you have shows
Software Recommendations :: 08-09-2015 21:23 :: SunnySkyguy :: Replies: 10 :: Views: 127
The standard is covered by the free "ieee Get" program
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-21-2015 15:44 :: FvM :: Replies: 5 :: Views: 698
Sarathkumarkj, you need to update your quiz to the 21st century. There is no longer an ieee Verilog standard. it has been replaced by ieee 1800 in 2009, the current revision is 1800-2012
ASIC Design Methodologies and Tools (Digital) :: 06-04-2015 15:14 :: dave_59 :: Replies: 8 :: Views: 2236
Just curious on everyone's opinion of numeric_std_unsigned in the recent VHDL2008 standard. The most cited reason against using std_logic_unsigned was its origin at synopsys, followed by concerns that the code would not be portable. Now that ieee has recreated (and updated) the package, will the advice be to move to numeric_std, or numeric_std_un
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-26-2015 19:32 :: vGoodtimes :: Replies: 0 :: Views: 587
According to this article, effect on frequency shift may be negligible if we consider the intrinsic standard error associated to crystal frequency:
RF, Microwave, Antennas and Optics :: 05-24-2015 12:53 :: andre_teprom :: Replies: 4 :: Views: 1434
Can somebody help me to find ieee standard for mm wave frequencies in Radio over fiber link?
I am using a 30 GHz wave in my radio over fiber link and I need to know what should be the power of my transmitted data? In the receiver side I need to know which sensitivity is acceptable for the receiver.
Your help is appreciated.
RF, Microwave, Antennas and Optics :: 05-20-2015 20:21 :: Natasha123 :: Replies: 0 :: Views: 393
in page 78 of ieee 159 standdard (1992) - table 10.2 : it was written that for low voltage application the voltage THD must be less than 5%.
my question is what is the exact value of low voltage? what is the range of low voltage? less than 100v ? or ....116001
Power Electronics :: 03-28-2015 12:48 :: zizi110 :: Replies: 0 :: Views: 576
While on the subject of typing, this massive load of package uses is a fairly standard way to confuse yourself (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-09-2015 08:13 :: TrickyDicky :: Replies: 2 :: Views: 895
Welll, exactly one trivial google and less than 10 seconds away:
1735 IP Encryption and Rights Management
As part of its Plug-and-Play IP initiative, Xilinx has adopted the ieee P1735 encryption standard to ensure interope
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-18-2014 12:28 :: mrflibble :: Replies: 3 :: Views: 1747
hi all. i am working on developing 100G Ethernet PCS based on ieee std.802.3bj-2014.
i am confused about the scrambler and 256B/257B transoder.
the tx flow described in ieee 802.3bj-2010 standard is below:
Encode -> Scramble -> Block Distribution -> Alignment Insertion
-> Lane block sync -> Alignment block removal -> Transode -> (...)
Digital communication :: 11-27-2014 05:21 :: ember.cc :: Replies: 0 :: Views: 721
can you help me to solve the below error
I am running vsim -t ps -sdfmin /tb_msp=output.sdf -c tb_msp
vsim -t ps -sdfmin /tb_msp=output.sdf -c tb_msp
# vsim -c -sdfmin /tb_msp=output.sdf -t ps tb_msp
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading work.target
# Loading ieee.std_logic_arith(
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-20-2014 05:04 :: abu9022 :: Replies: 3 :: Views: 2094
i am a student and got a project for "implementation of a channel equalizer for a wireless OFDM according to the ieee 802.11a and Hiperlan/2 standard."
i dont have knowledge about system level design environments for DSPs into FPGAs..,what i have is this ieee paper and nothing else,
i was unable to gain knowledge on (...)
Digital Signal Processing :: 10-08-2014 09:05 :: nick123 :: Replies: 0 :: Views: 712