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14 Threads found on Star Routing
How to extract spef from star rc...?? to my knowledge i think 3 files are necessary. 1 routed def 2 file for synopsys 3 rc corner please correct me in inputs if i am wrong. How to get rc corner file ?? if possible plz say me the inputs and where to get from ??
why to verify timing after routing stage in physical design? why to verify timing after star-RCXT Extraction in physical design? Please give me the answer
Hi all, I am using DDR3 in Flyby Topology but due to space constarint in board I have to place my DDRs one over another. What I need to know is can I place DDR3 in this way and have the connection of addr,command and control signals in star topology (like we do in DIMM modules) or do I need to maintain flyby topology for that. The addr, cmmd an
Pls keep large current path short and straight. Then connect small-signal ground to true ground by star connection with narrow wire.
Dear all, i know that i should be carefull in the way i route vdd and vss, but that's all i know, can somebeody give me the big issues with routing vdd and vss ps: it's an analog block i have heard about ground planes star connections, avoiding supply loops , can somebody clarify for me those concepts or/and give a good reference or link abou
I am routing a address line A0. It comes from the processor and connected to 2 DDR2 modules.i am following star topology. So I scheduled nets and formed a T junction.Now what i have to do is to match the length to each of the DDR2 what could be done to match the entire T connection. Pls reply sandhya
star topology is used for DDR2 designs chk out this one
Dear Sir, If your Astro file have CapModel or CapTable definition, it means you have tlu model for RC extraction in Astro. You can use it to do placement and routing. The .itf file is TLU+ model.(use star-RCXT transfer .itf to TLU+ model) The TLU+ model accuracy is more than TLU model. Best Regards, chyau
Hello board, I want to route a signal between 2 adjacent boards(track length is about 6 inch), output of board A will be input of board B. I deally I do not want to have difference between level of these two signals more than 10uV in two different boards. though I have used star configuration of GND and thick GND tracks(60 mil) for each board but G
you already askede in this topic: star topology or daisy chain.
If it is 2stage flash ADC, it should be fast ADC, isn't it ? So, single ended is a non-sense, because the digital will make a lot of noise that will come on to signal. If you keep on working with single ended, split as much as you can analog and digital, especially within the ADC. Split the power supplies, use star-routing. Finally fill any blank
If you are routing in single/double side PCB go for star or Multi drop routing topology. Avoid Daisy Chin. You dont have to worry in case of Multilayer board.Vcc Plane takes care of it. Good Luck
Filler Cells are used to avoid the Base Layer ( Nwell, PPlus, NPlus ). The flow is, * Insert the Filler cells once you're done with the routing & Optimization * Then dump the DEF from implementation tool. * Parasitic Extraction from QRC/star-RC * Timing Analysis using PT * If Timing Violations are there, then go back to the Implementation tool. *
Thanks a lot mate. Actually i am using cadence First encounter for routing. Now for doing manual routes for PLL's i was told to do routing in star formation. So thats why i was totally confused as to why this requirement was there. If any one else can comment it would be very much appreciated Ehh... you design PLL-