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61 Threads found on edaboard.com: Startup Bandgap
Hi Guys, I have a concern on the bandgap start up circuit design. I understand the need of a start up circuit in the bandgap design. But I'm not very sure, or need your feedback on the simulation outcome that Im observing. With the startup circuit added, the bandgap core output voltage is able to settle around 150us when (...)
This is your fundamental "box" for designing startup circuits. The startup current needs to be large enough to boot the loop in the worst case, and it needs to be low enough to not bother the loop setpoint in the "best" case. PVT can make this a thread-the-needle exercise especially if you want to stay simple (like diode-steered resistor pullup)
I would suspect that the Schmitt threshold is too close, but on the wrong side of, the bandgap output voltage and yet the startup circuit cannot be removed without the bandgap core collapsing. The startup looks too simple to me. Start with breaking that feedback loop and see where the startup can be removed (...)
You could start with just what "didn't work" means. A result you didn't like, or failure to produce a result at all? bandgap / PTAT loops without explicit startup mechanisms, can easily converge in one testbench and fail in another, because when they start up they're doing so on "numerical noise" which depends on the circuit matrix and algorithm
Add some deliberate leakage (a very low current source or large resistor) to prevent it starting. Then add the startup circuit and check it does start. You may be able to do it with "initial conditions" although I usually add deliberate leakage. Keith
It's a normal zero current startup circuit I think, and I want to use it in a low power bandgap. But someone told there's startup risk in real chip. Can anybody tell the detail analysis and how to simulate it. 78546
Hi Guys: I am working on a bandgap circuit for a internal regulator in a DC-DC converter. The core circuit is a simple BROKAW bandgap circuit and i need a startup circuit for it.The problem is the input voltage is from 5~23 and the high voltage MOSFET my process provide have a max Gate-Source voltage(Vgs) of 5,while the max (...)
this architecture is bad for low voltages. I like it since it is reliable. In your case you probably will have a bit high current through startup circuit - but you can fix it. Temeperature coefficiant - you can try to play with 1:n ratio. I noticed in my case that if I use usual 1:8 or 16, it does not work well so I went to 132 and made my own bipo
Node setting is cheating, and if your circuit requires cheating to work in simulation you will be busted in the real world. If your results are way off then suspect a startup problem. If slightly off, suspect a floating or unrealistically high impedance node somewhere that plays with the accuracy difference between tran and dc.
Will the bandgap ref work well if I add 2 cap and 2 res in the circuit? startup without any problem? stability for work?
Hi all, Could someone help me with the startup problem in my bandgap circuit? I have startup problem for lower temperatures .i.e if i simulate ckt for weak -40. I get output waveform as attached .. Thanks in advance rampat
hi all, i wanna do some research about the startup circuit of bandgap, please help me 1:how to analysis the numbers of the stable operating points of the circuit. as far as i know, some bandgap circuits have 2 stable operating points, some circuits have 3 stable operating points. I wanna know are there some methods to count the number
Hi All, I have a bandgap reference circuit, which works fine in simulation. (Both DC temperature sweep and transient sweep give satisfactory results.) As this is my first fabrication, I am a bit concerned about the start-up and also the stability of the circuits. startup the startup circuit I used is the one based on capacitor. (...)
First, what kind of fluctuations? One part, output varies over time? Or population of parts, with (say) a bimodal distribution that's being caused by startup ckt bothering / not-bothering the reference loop? You need to get the diodes "lit" reliably, to some fraction of the setpoint current but remove that influence once the output is c
Hi For 1.5V supply I would not use the classical bandgap approach The classical approach will show some serious problems in the low-temp/slow corners, especially during startup ... Look out for some papers about low voltage bandgaps. The basic idea there is, that you add a ptat and an iptat current. THis current is injected into a (...)
Make the startup current is zero during the dc analysis when the VREF is up at all temperature and corners. After that, try to tune the Temp Co.
In your LDO, the reference voltage could also took from the BG output to further improve the PSRR. But some effort must be made to avoid startup problem in this configuration.
Hi this bandgap the startup circuit works fine untill I apply an offset (vos) to the opamp. With a positive offset, all it's ok but witha negative one the loop becomes open! Why does it happen? Any suggestion to avoid this bad behavior, please? TIA, CBs
hi all, what are the design limitations for startup circuit in BGR? how to improve the startup time using the below circuit? Attachement is the Conv BGR and the startup i want to desgin....
hi, would you pls suggest a startup circuit for Conventional BGR,which consumes less current(in nA) and improves the response of the bandgap? Thanks
hi does self biased BGR requires a startup? THanks
I will do the tranisent simulation to test if it is stable when power on. Please take attention to the startup with different rate of power on.
Interessting problem... I know how to figure the waves and could also point into the circuit reason but thinking of the right differential equation giving the same response is tricky! The best start would be the loop gain equation of the kT-generator and using a first order integration. That should show the slow intial startup. The next point
1.what is your initial seting for your circuit or why you do that? Becuase you have an inable pin? 2. The mean state is a stable state and in this state the VBGR will not start ever without start-up circuit. I designed bandgap voltage reference and startup circuit for it. I have read topics about BGVR and startup. I verify start
Hi, I am trying to make sense out of the startup circuit of this bandgap reference design, but I have not been able to. Could someone please help?
Hi Surianova, Yes in this circuit u very much need the startup circuit... This circuit has two stable states one with zero current and other one with defined branch currents... and the second state is desired. So to pull it away from first state and pushe it into second one we need to inject some current into its branches
Hi, Are you having the issue in simulation(pre tapeout) or in Silicon ?I think bandgap is a self biased circuit and hence the circuit will either operate as desired (with required current mirroring + bg voltage generation etc) or will not startup. So in general , a startup circuit is added in bandgap so that it does start (...)
Hello, I'm looking for some startup architecture for my bandgap, can you give me some reference. Thanks
So it has only startup function? Are there any other function???
If you are doing a transient run then startup is required.If you do OP simulation then startup may not be required for the simulation. Jitendra Dhasmana.
don't know how do you break the loop at the opamp output. I uaually break like this. C2 and R2 are large enough, e.g 1Mf and 1Mohm. C1 is the gate capacitance of pmos current mirrors. The "ring" during startup is normal. There is always "ring" during startup. Noise is necessary and
OK give me also a try: 1. Use a bandgap VBDG=1.2V 2. At chip startup sample the ratio of VDD/2 to VBDG by using a opamp and a ladder network. 3. Use a comparator which compares the scaled VBDG with VDD/2 4. Use binary search to fix the scale factor 5. Finish the initial calibration. So the scale factor multiplies the VBDG to V
hi,all I have a doubt about trimming of bandgap reference which is showed in attached schematic.The R2 and R3 should be trimmed at the same time or only to trim R2 is enough. For trimming convenience, i tried to combine the M1&M2, but the perfermances were difficult to tradeoff nice. By the way, the opamp's bias current was cont
Lets see.... The startup generate initial bias current ~(VDD-Vth,p-Vth,n)^2 seems ok! But the reg opamp of the kT-generator see the impedance of the inital startup bias generator. So use ideal buffer with some real output impedance to isolate the effect. I suggest that oscillation if happen because of the impedance vanish for zero ohm and ini
hi, all: I have designed a bandgap reference,the structure which i adopted is traditional,namely, the opamp's output is connected to two pmos's gate to adjusted the current. Now, the output voltage is change 1.2mv in the range of -40-->125,the startup circuit is ok. The only problem is the overshoot and undershoot is too large(200mv)when add
go for the bekar book for startup circuit
Transient analysis is enough to simulate a bandgap circuit. but simulation startup must do rampup you can tyr it
bandgap reference voltage is ossilating before it reachs to ref level during startup. Help me to solve this problem.
Increase your startup helper current injection and switch it off after the bandgap reach near its full voltage.
The architecture of amplifier is from Op-amps and startup circuits for CMOS bandgap references with near 1-V supply Boni, A.; Solid-State Circuits, IEEE Journal of Volume 37, Issue 10, Oct. 2002 Page(s):1339 - 1343 Digital Object Identifier 10.1109/JSSC.2002.803055 Summary: The design of bandgap-based voltage references in (...)
Do you know any book or ref to design the startup circuit for bandgap both in cmos and bicmos process. Please advise. thanks
hi, i'm design a bandgap voltage and simulate it with hspice. how can i simulate and validate my bandgap design correct or not without using startup circuit? is it using .tran xx xx uis and .ic v(x)=xx to initialize some node to the specific voltage? thanks.
hi can anyone of u suggest me a good paper or a link to design the startup circuit for the bandgap reference. If u have the circuit then can u pls upload it. thanx in advance
I need startup circuit for bangap voltage reference and value for R1 and R2. VDDA=5V
startup times less than 1us and good PSRR (<60dB) from DC to some 100MHz is difficult indeed and sorry your question is touching the critical IP domain. There are solution, sorry I could not offer more.
There are few such materials about startup circuits for bandgap in IEEE. Where can I find relative materials? Thank you there is one start up circuit in the chaper of bandgap in Razavi's book
Does the brokaw-cell bandgap reference need the startup circuit?? Thanks
If a current reference circuit doesn't exit zero solution, does it need a startup circuit or not?
1. startup cap. 2. it must be compensation cap of the feedback loop.
How to identify the startup loop and bandgap loop ?