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100 Threads found on State Machines
As you say state to be familiar with hardware description languages, you'll know that a loop construct generates parallel logic rather than a sequence in time. The appropriate means to generate a timed sequence in HDL is a state machine. You'll probably have at least two hierarchical state machines, a lower level (...)
I have a DE0-Nano board from Altera, and I am planning to do a project with it this summer. However, I am not sure what projects are interesting or suitable, at my current level. I learned about debouncing, state machines, ADCs, LUTs, and UART through my courses. From what I read online, FPGAs are good for parallel tasks and signal processing
hello guys I'm trying to understand how to implement state machines using matlab function in simulink, can anyone let me know what the meaning of this statement " persistent state , state = x1_state(start, {x1unsigned, 2,0});" in the following code???? Thanks in advance. function (...)
i have been implementing the sequence detection of 1101 in system generator using "mcode" block that performs state machines , i have understand the other things in code, but could not get the meaning of this sentence "persistent state , state = x1_state(start, {x1unsigned, 2,0});" can anybody tell what (...)
Hi, I am using Dual Clock fifo from Altera IP Core and instantiating it as: rx_dcfifo rx_dcfifo_inst ( .aclr(), .data(payload), .rdclk(test_100_mhz), .rdreq(Rx_fifo_read), .wrclk(test_250_mhz), .wrreq(Rx_fifo_write), .q(Rx_output_from_fifo), .rdempty(Rx_fifo_empty), .rdusedw(r_depth_rx), .wrfull(Rx
You are willing to perform what is called a synchronous design and it is recommended you take a research on the subject 'state machines'. As it is your first design and the purpose is certainly learning, you will do manually the steps of the design instead using a tool for that. Basically, at the end of each functional block ( adder, multiplexer,
You can realize any kind of behaviour with either a Mealy or a Moore state machine. There are no restrictions on that. What will differ between the 2 implementations will be the number of states and the way outputs are generated.
I am not sure what you mean by FSM tools.....finite state machines.... it is basically verilog files which you write. Once verified, the RTL compiler(synthesis too) will automatically analyze the FSM state tables( remove the redundant ones) etc and up with optimal FSM state table. It will remove the redundant ones. very (...)
blocks containing FSMs in the form of one VHDL process for the combinatorial logic plus another VHDL process for the registers Come into the 21st centuary and use single process state machines two (or more!) clock domains, some with period X, some period 8X (i.e. a nice simple integer relations
Hi, I want to implement a digital controller for a switch mode power supply in Orcad pspice. The controller will take voltages and current values as inputs and create the control signal using intelligent algorithms (state machines, digital control techniques etc). Therefore I need a block that runs a code for processing these values (ie. C
I need help with his homework problem: Create a festive lights display with 8 light bulbs (B7-B0). When activated (A0=1), the appearance is of two balls bouncing off each other, as follows: 10000001, 01000010, 00100100, 00011000, 00100100, 01000010, 10000001, repeat. Each output configuration lasts for one second. Use bit-manipulation method
Hey everyone. I'm having trouble with this homework assignment. Here it is: A baby monitor system detects motion using a sensor (A0=1). The system should sound an alarm (B0=1) if no motion is detected for at least 60 seconds. A button (A1) or detected motion resets the system. Im supposed to design this using state machines on the RIBS soft
can any one help me... need mealy and moore state machines Design a FSM over { 0, 1, b } that will output a copy of the input string except that the first bit will have been moved to the end of the string. (?b? represents a blank? here ) E.g. . input : 010011 will produce output: 100110
I wish that people could stop talking about Moore and Mealy state-machines, because neither of them describe what we normally do today. Both of them have combinatorial logic after the registers, and that is not wanted with today's FPGA/ASIC architectures. They both have "input logic", registers and "output logic". The difference is that the Moore m
Can anyone help me out in making edge triggered Clock Adders & Multipliers in VHDL Hello Everyone, I am doing a mini project on Perfomance Analysis of Different Adders and Multipliers using XILINX Project Navigator 14.5 to write VHDL Code for the same but in that I am getting some errors. For that matter I ha
Can anyone tell me what is state machine in PIC micros and how ca I use it for LCD program?
Hi, This is very basic, but I am confused on this one. In the picture attached can someone tell what will be the state transition from E if it gets a 0 ? Its a 10101 non-overlap sequence detector. 102383 Edit: E -> A is 1/1
Hello there. Could anyone help me with translate this vhdl code to veriolog code? Thanks in advance. it is about 3 state machines. i know how to convert one state machine from vhdl to verilog but with 3 i cannot figure out what the states will be. type tx_sequence is (high_setup, high_hold, oneus, low_setup, low_hold, fo
First of all, I wouldn't get bogged down in all that "Mealy" and "Moore" nomenclature; that's stuff to just get you through college. I've been designing state machines for years and couldn't tell you the difference. Second of all, I would DEFINITELY advise that you use a synchronous design (is that Moore?). And if your state is (...)
hello are there a computer program that generate the code VHDL from state machine presentation? i think that this migration can be done by a computer program but i don't know if such program exist thank's