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25 Threads found on edaboard.com: Stb Simulation
Hi, below schematic is a fully-differential gain-boosting opamp that I'm working on right now. I want to check the stability of a local loop that is comprised of gain-boosting amp and a source follower. So, I inserted 'diffstbprobe (red color)' as below, set it as a probe instance, and ran stb simulation (for now, I'm using ideal CMFB, so (...)
hi,everyone: I'm doing a Complex BPF,but I don't know whether it is stable?How to determine its stability? I have done the transient simulation with a input of step signal,there is a ringing at the output, but I think the reason is large capacitances' charging in the circuit. Meanwhile, I have done the stb simulation (...)
Hi, Can ADS simulator do a loop stability simulation like spectre stb? Thanks!
I'm pretty sure at this point that results from AC analysis are correct, while those from stb are not. I've run time analysis with phase margin from AC near 45 deg and at that point circuit starts to generate. Why do you think that ac is correct? The LC method you have applied does not mirror the actual load. Thus, I don't know if this matt
1)~3) AC simulation or stb analysis 4) DC sweep 5) transient 6) DC sweep 7) noise analysis
Use "stb" analysis.
Did you use "stb" analysis? It is more accurate than "AC" analysis. Where did you break the loop? Pls also try to break the loop at N5, or N1, or N2. There are more than two loops. Stability is complex.
when I do cm stb simulation in three_stage OP,I add L=500p to power and ground. the result shows that a peak in f=9.6G. If I delete L in power and ground,there in no peak in cm stb result. Why? please help me. thanks!
Hello , When I use stb to analysis a multiloop circuit, for example-- a bandgap with the OpAmp topology. There will be at least two loops exist in the circuit, right? When I use stb to test the loop gain for one of the loop (loop positive), in this testbench--do I need to break the other loop(loop negative) ? The (...)
Hello, I did a stb simulation for a differential current input amplifier in a normal feedback setting. I put the vsource in one of the input node of this amplifier, then run the stb simulation to check the openloop gain and phase for the stablity, but I get a negative loop gain( about -50dB in DC, then increse to (...)
Hi all, Currently I am simulating my opamp loop gain char by using stb analysis. The simulation results looks good for pre-layout simulation and also post layout simulation extracted CC. The problem happen when I use RCC, RC and R extractiion netlist for the post layout simulation. The phase at low freq (...)
i guess what the stb simulation does is for the loop-gain, which will include the feedback factor. so the amplitude response in the bode plot will actually move up or down according the feedback factor, and the unity gain bandwidth changes..
Yes you can still use loopgain simulation methodology in cadence. However before running "stb" analysis you have to run transients till your CM is settled. An easier way is to use ideal CMFB circuit and then do can skip the transient analysis part. My answer assumes you already have good background simulation experience in spectre. Let me (...)
I have noticed, that the operating point is calculated as many times as many analysis need it. For example if one run a dc, an ac and a stb simulation, the operating point will be calculated 3 times. ........ An operating point is one specific point within the dc analysis. Thus, it is NOT calculated in advance because it
Replace the short between node VBE and the gate of TP8 with a dc voltage source (V1) with dc=0. Do a stb analysis pointing to V1. This should tell you the dc gain, PM and GM of the loop. To confirm it in the time domain, apply a small step disturbance on the supply (when the nodes are stable) and see how various nodes jump and settle.
Hi all, What's the difference between iprobe and voltage source with dc=0 ac=1 in stb analysis? I did the stb analysis using iprobe and voltage source with dc=0 ac magnitude=1 to break the loop seperately. The simulation results are the same. What's the difference between them? Regards, Colin
In Cadence, you can use stb analysis to do AC simulation.
There is a bandgap used self-bias cascode current mirror. Could it be needed to do stb simulation? And if it's needed, how to do it ? thanks
hello, for the AC sim of LDO, you can use RC technique described in philip allen's book (cmos analog circuit design) or iprobe with stb analysis in cadence spectre. both simulations will find open loop gain and phase margin of your LDO. make sure that pass device in LDO always operates in saturation region. hope this helps.
I have a problem with iprobe when put in hierarchy and then defined it in stb analys. ADE generate error window with title- "Choosen Analyses Form Error -specterVerilog5". And in window "Couldn't find component named /I33/I67/IPRB0" . I need gelp