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14 Threads found on edaboard.com: Structured Asic
What does sea of gates mean in structured asics? If it is related to number of free transistors (PMOS and NMOS) then can we program these transistors i? Can it be helpful in developing logic at transistor level by programming the transistors limbs' interconnects.
Same thing - programmed by metal at the end. The difference is the structure of a gate array is a simple, repetitive "sea of gates" whereas a structured asic can have a more complex structure. Keith
Hi Guys, for latch array or gate array place ad route, is there any good guide line or skill?
thank u! I think that structured asic is a good idea . especially for small IC fabless company.
Hi all, I just looked into and found there design flow picture. In that picture is shown that it is posible to make sinthesis using Magma or Synopsys. After synthesis next step is placement and optimization. But only Magma is shown there. If someone has experienc in structured asic design flow tools please let me know is it posible
Hi friends, Can any body provide usefull materials for the structured asic design flow.Websites alos. regards sreedhar
asic cannot be reprogrammed...from ur question, it looks like u were referring to structured asic ...check and Xilinx or google on working of structured asic... Is there what is called "Reprogrammable asics"? i.e. asic which can be reconfigured ? Even at the fab ? I (...)
Hi eda techies, Good morning,I am here by reqesting all,in finding out good materials,websites for structured asic design.
hi, In structured asic: 1. here only interconnect is customized 2. it contains base cells(sometimes called as primitive cells) and custom blocks are embedded. 3. manufacturing time is varying from 2 days to 2 weeks. In FPGA: 1.none of the m
i was recently watching a Synplicity Video on structured asic which they call it ISSP. They said that ISSP-1 which is first generation structured asic, has 200Mhz core and 300Mhz local frequency, where as ISSP -90nm has 340Mhz global and 500 Mhz Local frequency. My question is, what is this local and Global Frequency? (...)
structured asics are those which are similar to Cell based asics.. take a look at cud be arrangement of the cells.. but seriously asics and FPGAs are entirely different. with regards,
When targeting a structured asic, is there a technology file that is provided by the vendor or some other way to find out approximate gate counts? I'm doing a SOC and would like to know what the counts are of the currently completed modules to know what kind of space i have available to me. jelydonut
Does anyone have any info on the flow? Is there libraries available.. what tool would it be routed in (Enc0unt3r?) or is it done by the structured asic company themselves? jelydonut
Synplify asic is much faster. Personally I don't know anyone who has actually gone to silicon via asic, apart from structured asic designs. Obviously some people have, but if you can afford a DC license would you take the risk on the new kid on the block? Magma and Cadence buildgates (or whatever it's called this (...)