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35 Threads found on Sub Adc
We know that there are three situation of sub-adc for this title State 1) Vin>+Vref/4 State 2) Vin<-Vref/4 State 3) -Vref/4 Vref+ - Vref- (Vin+>+Vref/4 and Vin-<-Vref/4 subsequently) Vop of comparator is 1 and the (...)
I am designing a time interleaved at 800MHz. The interleaving factor is 4. Therefore each sub-adc should work at 200 MHz. Input frequency is 200MHz. Now the question is to find SNDR of the sub-adc at 200MHz. The problem is if I apply this frequency i would get a dc output. So, I chose a frequency near to the 200MHz such (...)
HI I am working on a 4 bit pipelined adc . I am using two 1.5 bit stages and one 2 bit stage with a flash adc . The two 1.5 bit stages include sub-adc , sub-DAC and MDAC . I am using one SHA at the input . I ran different simulation . First I tested the 1.5 bit stage independently . With real blocks and its (...)
i come across a problem on the selection of common mode input voltage. The OTA (shown in fig1)is used to implement the SC S/H circuit in pipeline adc and the subsequent MDACs. The supply voltage is 1.2V and the output common mode vlotage is supposed to be 0.6V. If I choose the Vcm,in also around 0.6V, the input transistor could hardly turn on for t
Hello rvs, Your LM35 can measure -55C to +150C with accuracy +1.5C and output scale 10mV/C. Your adc has 8-bit resolution with a maximum of 256 (28) steps. So, for Vref/2=1.28 Volt, you will get a full scale value for Vin=2.56Volt=2560mV. Rem
what is your adc sub-routine? is it interrupt based or poll based? share the main program.
hi i am a beginner in analog circuit design.. I am designing a dynamic comparator for pipeline adc in 90nm Cmos technology shown in the figure.. 1.8V supply voltage(Vcm=0.9V).. This dynamic comparator is to be designed for 2.5 bits flash sub-adc.. I have several questions.. 1) How to choose the value of Vrn and Vrp? 2) How to select (...)
Let's say the Open Loop Gain (AVOL) of two op-amps is 10V/mV and 10000 V/mV, respectively. The one with better performance will be used to build the signal-conditioning circuit (e.g. buffering, low-pass filter, etc.) for an analog-to-digital converter (adc). How will the AVOL affect the performance of an AD circuit? Which op-a
when i create a 2bit flash adc using schematics in tanner tools its power comes as 70mw but when i create the same circuit using sub circuit in tanner tools netlist the power comes as 77mw why does the power increases using sub circuit??? any suggestions???
HI all, I have a track and hold followed by a source follower buffer (on silicon) and i have been testing it and seeing the output on an oscilloscope. Attached in one of the outputs i see. It has input signal of 100MHz and sampling frequency is 20MHz ( it is sub-sampling for the purpose of time interleaving architecture in adc) . The think th
Hi experts, I am trying to design a dual band digital GSM repeater operating at 900 & 1800 MHz bands. It should have options of choosing at-least 3 sub-bands each totaling 25 MHz for GSM 900 & 60 MHz for GSM 1800 MHz band. It would comprise of mixers, LOs, Filters, adc/DAC, DDC/DUC which will facilitate flexible sub-band (...)
I design a SC Sigma-Delta adc for audio application as showed in the attached Figure. The adc is designed to work under supply voltage range of 1.6V to 3.3V and clock freq. of 2.56MHz. I have fabricated 2 chip for testing. - Chip01 with the VDD/GND are shared for analog and digital sub-locks. It works well with VDD = 1.6 ~ 2.2 V and Fclk (...)
Hello Everyone, what are the hot research topics in sub-threshold Analog CMOS circuit design these days? My Masters thesis is on designing adc at 0.8 V and now i started PhD and am implementing the adc in sub-threshold. What would you think the best topic for PhD considering the research going on? All comments and (...)
Hi, there, As is well known, the comparators in the sub-adcs of a 1.5b/stage pipeline adc can tolerate offset error as large as Vref/4, but why is it that ? can someone explain in more detail or post some links here, thanks! Added after 16 minutes: AND I also want to know which is the FIRST paper
subsampling adc has a reference generator. The sub sampling adc samples RF signal @ 100MHz. In such a scenerio should the Power supply of BGR be isolated by the supply of the adc? When integrated, the BGr is not working along with Other blocks of adc. any help in this regard (...)
The story is very simple: Design w/o considering mismatch effects. Then you can use near minimum area devices. Tolerate miss decisions in comparators because of noise. If your design have error correcting headrooms. Pipeline is ideal to implement error correction and calibration. All new sub-100fJ/Decision result are based on these two ite
the first stage second stage thing you are talking about is confusing me.... i'll explain in the way i know hope it helps... the sub adc(comparator) uses a clock which is a little earlier known as early phase clock.... i have worked on pipelined adc and i needed 4 clocks.... the early phase clock is needed because the comparator output (...)
i'm designing a pipelined adc (1.5 bit per stage),in the first stage,i find a strange problem;when i simulate it with vdc source in terminal of vdac+ and vdac-,it works properly;but when i added the sub-adc(two comparators) and dac(which generates vdac+ and dac- through output of sub-adc),i find that the (...)
Hi, Assuming your interrupt sub procedure is correct, you have to : 1. Connect a Normally Closed switch from RB0 to ground and not to RB5. 2. Select pullup and Interrupt edge ( falling edge) bits in Option register. 3. Use a debounce delay in interrupt routine, and then start interrupt code. 4. Since 'a' is getting incremented in the in
I will design 10-bit 10MSa/s CMOS Pipeline adc. Which references will you suggest me ? How can i start my design? I need help who have experience in pipeline adc design. Give me advices about sub-dac, sub adc, and the other components in pipeline structure. Thanks