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66 Threads found on edaboard.com: Substrate Resistance
Hi, I'm designing inductor model in CMOS process. I found few formulaes online for the model. The resistance for silicon substrate is given by Rsi=resistivity *2/(w*l) where w and l are width and length of the inductor. I'm getting the value around 36 Kohm. Is it right?
P substrate is a common node (distributed resistance mesh) across the circuit and every switching transition kicks it with displacement currents (Cdb*dV/dt). These currents may not entirely return via the ohmic ties. They may at least modulate nearby channels (body effect) and enter circuit response. A deep NWell gives an additional layer of junct
There are more than one ways to do that. QRC substrate handling methodology has been changed sin 8.x - there are detailed and good technical reasons backed by many big design house and fab. In new versions of QRC, the back-gate of MOS will get ideal VSS/VDD - by default, unless prop
Hi Folks, Can any one explain how tap cell is used to prevent latchup effect. I know tap cell is used to connect n and p substrate to Vss and vdd respectively. In google I found one more definition tap cell is reduce resistance between vdd and vss. Thanks in advance, kpsr
How do you connect the substrate? Every building block I use has a separate net for Vdd, Vss and Vsub. The Vsub net connects to the Vss pad using a star connection. Since I assume that the substrate doesn't run any current, this is a small connection. Is this correct, and if not, what kind of resistance is allowed from a building (...)
Hi everyone, I have one question about the dependence of parasitic of MIM cap on substrate contact resistance. I am using IBM pdk. I found that the parasitic of MIM cap in this process strongly depends on substrate contact. Please take a look at attached image: 103002 The parasitic of cap is very small if the subc i
This all depends on the signal attributes of interest. Typically upper levels are thicker and may have looser layout rules (esp. in RF and power oriented processes) so routing on M9 will cost you density. Routing on M1 will cost you more series resistance, capacitance to substrate, and impose a lower max current density (metallurgy being equal, w
My experience is that a LDMOS device standing off 20V, has better on-resistance than a standard FET stack of equivalent capability. This is, perhaps, because the LDMOS drift region is modulated to higher conductivity when "on". If your LV devices don't have a well that is independent and can be biased to (say) 17V from substrate, you are stil
Have an interesting Cadence error, after running DRC, "Has Multiple Stamped Connections". I know what it is, something to do parasitic resistance calculations on more than one substrate connection. Any idea where I can find the info to fix the problem, already tried Cadence help and Google. Have you seen this error? This circuit is an inverter circ
I can't set TFR properly in ADS momentum. Why? For the layer with your thin film resistors, you can set the sheet resistance (ohm/square) in the Momentum substrate settings. One example for resistive sheet can be found here: examples > Momentum > Microwave > ThickCond_Spiral_prj
Hello, I would like to know if anyone has a relatively easy way to estimate the resistance through the substrate between two closely spaced rectangular substrate-contact rings (P+ diffusion in a P- sub). The length/width of the rings can differ. below is a diagram to help illustrate what I am addressing: Any help would be g
or is it because the R given in the IE3D simulation is actually equivalent impedance? Yes, that's it. For example, if you simulate a transmission line or inductor over a lossy substrate, an extracted simple pi model will have negative series resistance at higher frequencies. That is because the simple p
hi how to reduce insertion loss in a power divider?? Reduce conductor loss and/or dielectric loss in the substrate. For example, FR4 is really bad for GHz power dividers because of high dielectric loss. tuning the resistance value did not help The resistor in a wilkinson
I think you can add substrate resistance modeling by using the resistance SHEET statement, but not capacitance.
Why substrate terminal is needed ,if we make any device like MOMCAP ,resistance?
How to add chip resistor in microstrip antenna (which is to short ground plane and patch) in ADS????? Draw a resistive sheet in layout (layer resi) and include it in your Momentum substrate definition, with the correspoding ohm/square sheet resistance. You can also use the TFR element if you prefer to auto-gen
When you extract lines over lossy silicon substrate, and interpret results as a PI model, you will indeed see negative series resistance at high frequencies. This is caused by current flow in the lossy substrate and indicates that your PI model with only one resistor for series loss is somewhat too simple for this case. Of course, laws of (...)
Hi all, I am working on Ansoft HFSS to simulate a spiral inductor. I dont know how to extract the circuit model parameters like Rsub(substrate resistance), Csub(substrate capacitance), Cs1, Cs2, Rs etc shown in foll. post if u have any idea or formulas. Thanks i
The bulk resistivity of SiC can really be variable depending on the fabrication process. But a reasonable assumption would be values of 1e4 to 1e8 ohm-cm. It's a pretty isolating substrate anyway...
It's normal.. Output impedance is operating point dependent parameter of an active device. Intrinsic capacitors are indeed variable capacitors with applied voltage between-for instance- drain and substrate and that's why they are Vds dependent. Similarly, Instrinsic output resistance is not a fixed resistance instead a variable (...)