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101 Threads found on edaboard.com: Subthreshold Region
Can anyone help me in designing a source degeneration OTA (MOS) in subthreshold region? I know the equation of subthreshold current but from where to get Io value and n value?
Can anyone help be in designing a simple OTA in subthreshold region. The Current equation I know is ID=Io x e(VGS/nVT), what will be the Io? and how can I design the OTA?
How do you ensure that your operating point stays where you want it? That's the first trick. As VT slides around with temperature, are you then requiring that the circuit (centered at some subthreshold point) really work from cutoff to strong inversion when you throw PVT into the mix? Second is to be really sure that your subthreshold (...)
Can we intentionally design& use mosfet'sin subthreshold region in a circuit(whatever the circuit)? Because in subthreshold region , we can get high gm/id? Is there any drawbacks, ofcourse slow in speed?
Hi i designed an analog multiplier. I found a lot of works on subthreshold and saturation mostly as compared to triode region. In general why not in triode region. What are the general disadvantages regardless of the multiplier circuit design. Becoz if multiplier is required to have a linear operation then triode region (...)
I'm working on a circuit that has two subthreshold diode connected transistors. I believe these two devices have the most impact on the variation in the circuit (with a Monte Carlo Analysis). I think it would be due to the exponential dependence on threshold voltage in the subthreshold region. I've managed to reduce the effects of process (...)
I want to try "subthreshold region operation for M5 (simple method)". I have attached the screenshot of my design where i achevied min ICMR of 1V but i need to get it to 0.6V. My design is based on 180nm technology and VDD is 3.3V. Seems you have NMOSFETs with a very low threshold voltage available: V(V3) - Vs
Hi all i am working on subthrshold region using pfet. I have done this before using nfet and using voltage source. I have good idea abt nfet where VGS < VTH and VDS can be neglected no matter wat the value is if its above VTH. But could anyone pls tell me how is it for pfet transistor. In nfet i used two voltage sources VGS and VDS and biased the t
... And I want to use the LL transistors for the digital blocks. I also want to scale the VDD of the digital blocks to operate them in either in cutoff or subthreshold region. Will the power dissipation for the digital blocks be reduced if I follow this method? Sure it will, but their max. operation speed as
Just to put a little more theory to this discussion - in the subthreshold region, source/drain current in a MOSFET is described by the following functional relationship with threshold voltage Vt: Ids ~ exp = exp where e is electron charge, Vg is the gate voltage, Vt is the threshold voltage, k is the Boltz
Hi All, I am designing a two stage miller opamp (pmos input differential pair) in subthreshold region. I am using 32nm technology node. The parameters are given below: 1. Supply voltage = 1V 2. Bias Current = 200nA 3. Transistor Length = 160nm=(5 Lmin) There are no specific requirements but I have to just reduce power dissipation. I am gettin
I'm trying to design an ADC in subthreshold region of operation of the MOSFET. It should consume least amount of power. I searched the web and found ADC types - SAR, Wilkinson, Dual-slope, ∑-Δ, Flash, etc. I also found a paper entitled "An 8-Bit Single-Ended Ultra-Low-Power SAR ADC With a Novel DAC Switching Method and a Counter-Ba
I am currently designing a ring VCO in CMOS subthresold region of operation. The output level of the VCO varies from 0.5 V to 1 V (VDD) with frequency of 50 MHz. Since all the MOS are in subthreshold region, their output resistance is in the range of MegaOhms. So my VCO output resistance is also in MegaOhms. Can you help me design a c
Thank you, SIDDHARTHA HAZRA. Relating to M9, you are right. I can't make it operate in saturation region. It is in subthreshold. I saw that current mirror in this patent and the article says that it is better. I used this structure for that reason. ...
... whether it is in SATURATION or subthreshold region. subthreshold is not a region, but an operation mode. A MOSFET can be operated in subthreshold mode (Vgs < vth) and simultaneously in SATURATION region (Vds > Vds,sat).
If you don't need the last bit of headroom then subthreshold wastes area. One other issue is, how low can you go before leakage currents become too variable (process, temp) to keep mirror fidelity. The higher your upper temperature limit, the less deep into subthreshold you can reliably go while keeping matching or even gross setpoint. Wider
How to represent mosfet in triode and sub threshold region. like self cascode transistor one transistor is in saturation and another once will be in the triode region . i want to calculate output resistance and effective trans-conductance of self cascode MOSFET. can any give the brief note about this topic. thank you
Hi, I am working on the design of some subthreshold circuits based on TSMC 0.18 cmos process. But there is huge difference between the simulation and measured results. I designed a regulator(power consumption=1uW) based on the subthreshold voltage reference proposed in the paper "A 300 nW, 15 ppm/ C, 20 ppm/V CMOS Voltage Reference Circuit Co
subthreshold (or weak inversion) actually isn't a region of a MOSFET's output characteristic like off, linear = triode, saturation or breakdown region - which are identified by a Cadence ADE analysis, (together with No.3=subthreshold) - but much more an operation mode, classified by the deg
maximum load current=50mA I m getting this output voltage but Pmos pass transistor is going to sub threshold region. Vref=1.16v. ... what should be done to operate it on saturation region Hello kishore, subthreshold is not an operating region (meaning a region in the output characteristic