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Switch Cap Simulation

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23 Threads found on edaboard.com: Switch Cap Simulation
Hi all I have completed the design of the basic S/H stage of a 1.5Bit pipelined ADC converter (VDD=1V, Fclk=40MHz, Input signal swing 0.25V-0.75V). After simulations i have noticed that when the input is quantized, except the steps in the output i get spikes during the transitions of the clock which can be as large as 50-60mV. Is this normal
Hi switch cap use clock for get equ_R valuse , and I simulation AC response by this method .. but if clock have gitter .. how to simulation it in hspice ... in .tran simulation we can monitor switch_cap and get a "resistor value" but in (...)
may i the detail of using @ds in switch cap simulation? you mean @gilent @ds?