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35 Threads found on edaboard.com: Switch Capacitor Simulation
I think I figured it out... the CLK gives half second 12V pulses, the relay coil remains energized for about a second, or if I dont switch off CLK 130493 You have the right idea. My simulation had scope traces which showed the capacitor discharging slightly between pulses (CLK). If the pulses
I guess, specifying the switch closed at t = 0 means it's already closed at startup. Should specify a very small time offset. Secondly minimum conductance constraints of the SPICE simulator might cause a problem in some cases. Adding a gohm leakage resistor the the capacitor might help. Finally, check that the switch doesn't have a (...)
Probably either the Native MOSFET's or the switch's model (or both) aren't correct re. the parameters which determine the leakage value. Anyway, for such analysis you should always use the lowest possible value for gmin (10-15).
I believe you are connecting the switch that is driven by phi2 wrong. Check it to make sure. Other than that, I can give you some friendly advice that might make your life easier: 1- If you are not going to model and opamp, just use vcvs, simpler, easier and more reliable. 2- You are giving way long non overlap time between signals. It might
thanks, kennambo. in theory this is well understood, in switched-cap we also simulated with clock, no problems. I just first time to do transient simulation check with a constant voltage. yes, it is like a diode connected, it always at saturation region since the gate and drain are connected to VDD, the effective resistance of the NMOS is relat
gm/Id is mostly for DC operating points and small-signal parameters. switched-capacitor circuits will require a transient simulation. You may get a good starting point with gm/Id, but you'll have to do simulation-based sizing (tweak-simulate-tweak) anyway, maybe with an optimizer software, and could start with it right away.
Hi all, during the simulation of the sample and hold circuit, i have encountered one problem. the circuit is a simple sample and hold circuit consisting of a switch and a capacitor. the input is vsin with pac mag set to 1. after simulation, when the sampled voltage at the capacitor becomes 0.5 instead of 1. (...)
Hi, I meet a problem of convergence when I use veriloga to model the SH circuit. I first use veriloga to build the model of capacitor, ideal switch and ideal opamp, but when I do the simulation with spectre, It tell me no convergence, how can I do with this problem? thx!!
I would build a separate testbench for this AC analysis. Just the switch-able capacitor and a (perhaps verilog-a) control block that selects them. If you do not like the previous solution, you could also write an ocean script and go thru all the codes.
hello friends I have designed the folded cascode opamp...(fully-differential)....i have added SC-CMFB circuit to Amplifier ....but i am getting problem in simulating with PSS and PAC analysis.. my detailed steps for the analysis are as follows... set pss simulation for clock of 2.56MHz and input signal of 256K
Should your project be something novel ? or you can simulate some devices which are already designed (ex: RF switch or variable capacitor).
Yes, with 10mA current source, the OP output will saturate in about 100 ns. So it's somewhat mysterious what you want to achieve with this circuit. In simulation, you may want to use an ideal switch provided with all common SPICE simulators for the time being. A MOSFET can be connected across the capacitor, but the gate capacitance will (...)
Use an analogue switch to charge the capacitor. Buffer the capacitor with a CMOS or JFET input opamp. Keith.
Hi; I want to measure frequency response and phase margin of a switch capacitor circuit by simulation. I think it is impossible with HSPICE. Do you know any software or method for doing that? regards
Hi Folks, Problem statement: Circuit: 1.5v DC ideal voltage source connected to a 1pF capacitor through a CMOS (transmission gate) switch. switching frequency 100nS. Transient sim run for 50 clock cycles and the average of the hold state noise voltage taken over these 50 cycles. Run eldo noisetran statement as follows, (...)
Hi, I am designing switch capacitor blocks (integrator, filer, amplifier) and need a help. Since SC circuits are time-varying ones, it is not possible to use direct small signal AC analisys in hspice to plot/analize frequency response. Theoretically I know there are different methods which translate the time domain to frequency domain, or ther
I designed an analog switch. The switch is T type, which is composed by 2 T-gate and a NMOS. The PMOS W/L is about 35000um/0.5um and the NMOS is 7000um/0.5um. That means the on resistor is very low, the test results is about 2.5ohm; but the paracitic capacitor is very large. The BW simulaiton results of this analog (...)
I wonder how to simulate switch capacitor circuit such as SC filter 's frequency response in ADS , in cadence I can use PSS and PXF , but how can I do it in ADS?Does anyone know it ? Thanks very much!
can anyone tell me how to measure the switch's turn-on time and turn-off time using hspice simulation? thanks
If its only simulation, use a super big capacitor with the positive pin connected between the switch and the led and the other pin connected to gnd.
Hi jerryzhao, I faced the same problem for my switched capacitor ADC some years before. The problem was that when the switch was off there was a division with zero that was not allowing simulation to run. The best workaround I found was to simulate the switch with a voltage generator or a voltage (...)
There is no better tutor than working on a real example! Create a switch that drives a resistor. Work on all possible simulations ( mostly transient). Add a capacitor ( now you have a filter). Do the same. Try now switched capacitor by implemnting a logic ( a pulse generator) driving the (...)
ac cannot simulation it. use resistor to replace switch cap.
in the picture,when phase 1 come, Vcm and Vbn create a voltage difference on the capacitor,when phase 2 come,the voltage difference is feedbacked to the lower transistor pair,and phase1 and phase 2 do not overlap but the simulation gives this result, periodic output dc level and some ripp
switch ON Vcc from 0 to 5V at the beginning of simulation.
for the OPA with swith-capacitor common feedback, it is controlled by two clock signal, how to simulate the bandwidth and gain of this type of OPA to replace the switch cap by large resistor can smooth the simulation
Go to the JEDEC site and download the test specification: All it is is a precharged capacitor, a switch, and a resistor.
You can get Ronn by par('V(in,out)/i(Mn)') and Ronp by par('V(in,out)/i(Mp)'). The Ron=Ronn||Ronp. You may add a load capacitor at the output of your switch.
Dear all: I designed an AMP with switch-capacitor CMFB. but i don't know how to simulate the open loop gain and GBW of this AMP. When i do this simulation,i replaced the sc CMFB with an ideal cmfb in the AMP,then i can get these results,but i don't know whether these results are the same as SC CMFB. Another quesition is how can i (...)
Hi, Transient simulation (.TRAN) is well-suited for this kind of circuits if your DAC is described at transistor level. And if you use sigma delta, the best way is to choose the Eldo switched capacitor macromodels. Eldo offers many possibilities, it depends on your application. I hope it helps you ... Bozzo.
There are some switch capacitor circuits, for example SC filter, SC samp-hold circuits. How can perform AC analysis for these using spectre and hspice.
I guess you had "switched capacitors" in mind. In this case here is a link to the relevant web site: regards ..
I think this topic appeared in this forum several times during the last couple of weeks! Go to and read Ken Kundert's paper "Simulating switched-capacitor filters with SpectreRF". You'll find everything about SC filter simulation with SpectreRF there!!
I am design a switch capacitor circuit. I want to know how to simulate the noise of the circuit. First i want to say the hspice commond (like .noise) is not right for me. I try a low pass filter of SC , then the result of noise simulation is mistake. In the theory , the noise is KT/C, but the figure is not agree with the equation. So (...)
may i the detail of using @ds in switch cap simulation? you mean @gilent @ds?