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37 Threads found on edaboard.com: Synopsys Design Constraints
Did you mean if I use "-clock_fall" in the commands, then does it mean I want to use dual clock? It meas that you are trying to put a constraint on the falling edge of the clock. For creating clocks, the " create_clock -period 5 clk " will suffice. So no need to use... create_clock -period 5-waveform {0 5} -name clk[get_
Dear all, Thanks in advance for your help! I have synthesized my design in synopsys design vision, at first I create the clock to 10 ns, and the timing report showed that slack is 0, and the critical path is one bigger multiplier. Then I changed the clock to 4ns, this time it took me more time to synthesize my (...)
Dear all, I am trying to perform clock gating for a submodule present in a bigger design. I want to disable/enable the clock to this submodule depending on a control register. The module I want to clock gate is MB as shown in the attached figure. I implement this is verilog using and AND gate as shown and synthesize using synopsys (...)
is synopsys' user online support.
I run synopsys design compiler for a relatively large processor core and every time I get a different netlist. Is there any why to get deterministic results from this tool?
I have a design that contains redundant structures and I do not want synopsys DC to optimize my design logic away, but the tool remove the circuits by default. How can I ask DC not to remove my logic? Also how to reduce the optimization effort? (I have very relaxed requirements for other constraints.) Thank you!
Hi, i would like to get the low standard cell size for basic inverter, but am getting little higher. How do i reduce the standard cell size(Trnasistor size up to Pmos -0.5uW/0.65)? also our software has no these Maximum (and minimum) capacitance, Cell degradation in design Rule constraints. Thanks in advance.
Hello Can we apply XDC "Xilinx design constraints" file -which is nearly similar to SDC "synopsys design constraints" in syntax and commands- to XST "Xilinx Synthesis Tool" in ISE, instead of applying the XCF "Xilinx constraints File" or the UCF files ? In case the answer is no, So (...)
Hey, Synthesis is not just converting RTL or higher level design into lower level (mainly gate level). Synthesis tools like synopsys design compiler also do optimization of your design. There are various algorithms which are followed based on the design and constraints put by the (...)
Hello i am using synopsys design compiler and cadence encounter to create a chip. i have a question. i am at import netlist phase. which commands i need to use at synopsys design compiler so the netlist that will be produced be the right one for encounter? here are the commands that i use: analyze -format verilog (...)
design rule constraints in synthesis, try look at the table in this blog:
Hi all, I am trying to synthesize an asynchronous block with synopsys design Compiler. My design is correctly elaborated by the tool, but when compiling it "optimizes" the architecture modifying the netlist. For instance a XOR2 can be transformed in AND + OR gates, or multiple gates can be re-arranged to meet certain (...)
Hello, My design has 2 different and independent clocks. So I constraint it using: set_clock_groups -async -group clock1 -group clock2 set_ideal_network set_ideal_network After loading the constraints, I got this warning: Warning: Clock port 'clock1' is assigned input delay
Reads existing synopsys design constraints Files (.sdc)— with all current constraints and exceptions— that are specified in user-defined order in the Quartus II Settings File (.qsf). If a synopsys design constraints File is not specified in the Quartus II (...)
see synopsys SDC constraints documents , SDC is original synopsys format , now is open format , accepted by all vendors ,
SDC - synopsys design constraints This file is used for all implementation tools starting from synthesis, timing analysis, place&route,dft,fpga..etc. This is very important file to ensure proper operation of your design, fpga, silicon SDF - Standard Delay Format Used to convey the timing information of a (...)
Hello, In a design for a class (a bad design IMHO, but I have to deal with it...), a chip access an external asynchronous memory. Therefore, there is a path from the transition of addr rd/wr signals to the output pads to the async memory to the input_pad to the input registers in my chip. My problem is how to tell synopsys about that (...)
What are the constraints tool consider from SDC before and after CTS ?? If there is any good document about constraints please post me a reply??
Hi guys! I'm learning Digital design with design Compiler and I want to know more about timing constraints and optimization. synopsys has published an excellent user guide named "synopsys Timing constraints and Optimization User Guide" but unfortunately it's in our uni's computers and (...)
Try this site. There is all kinds of information on how to write SDC files, tutorials and etc....