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94 Threads found on edaboard.com: Synopsys Primetime
Hello, I have just started learning primetime tool Can someone tell me about library files that are to be included with the design? Do we generate those lib files or we download it from company websites,I got mixed messages, somewhere I read that we create these files using lc_shell, and ncx etc. whereas some posts suggests downloading it from
I had a quick question about synopsys primetime (PT). I need to trace the connectivity of a design in PT *before* an update timing is done. If I call all_fanin, I think it will trigger an implicit update timing (bcoz all_fanin is documented to trace back the fan-in up to the start of a *timing path*), isn?t it? If so, that?s undesirable. Any
Hello, is there any way to set pin capacitance or pin transition time at synopsys DC or primetime? Moreover is there any command to set minimum_transition?Like the set_maximum_transition command.. thank you.
Hi, I am a new user of synopsys primetime. I have a verilog design. I want create an SDF File with primetime, but the tool give this error plz someone can help me to resolve it : pt_shell> set search_path pt_shell> set link_path * pt_shell> read_verilog tb_b01_AB.v Pre-processing Verilog file '/auto/zourgani/Bureau/B01/tb_b01_AB.v'
Hi, I want to run power analysis in synopsys primetime, and I have generated the netlist and the sdc file of my design as well as the vcd file from modelsim. But when I run the primetime, there?s such error: Error: Can not find any event in the event file. (PWR-248) In the generated power report, the power is 0. So what does this (...)
Could any1 plz share some detailed documents about OCV,AOCV,POCV,timing derate the basics atleast,It is very useful to me It comes from document "primetime Parametric On-Chip Variation Application Note" of solvnet, So you need to have a synopsys Solvnet account! Login there and just download related documents. Sinc
Hi all, So I have a combinational ckt(Benchmark c432 ckt to be precise) and I want to find out its critical path using synopsys primetime, because it is a combinational circuit it does not have a clock so after reading the design I used the create_clock command in primetime to set up a virtual clock(not sure if it is the right step). After (...)
I had done the timing analysis of a counter in both synopsys DC and primetime, but got the same output!! Any problem ?? Design file used is counter.v The design compiler output is attached as DC.txt The primetime output is attached as PT.txt Design co
Look for the cells, which had more than 200-300ps delay and have more fanout or cap value. Those are the cells need to be targetted to replace to get good timing values. report_alt_lib (in synopsys) gives alternative lib cells.
Hi: I have a question about STA. I am using synopsys primetime . Currently, I have a design netlist, SDF and SDC constraint. There are some clocks define in SDC file. I want to know the real time that clock arrival the D-FF's clock pin. It should be clock pulse time + latency. Right ? How to use one STA command to know the real arriv
Hello, I have spent some time trying to figure this out. I am synthesizing and analyzing circuits with a typical synopsys Flow. I am doing post-layout timing analysis with primetime and have spent a bit of time digging through the manual trying to find something that is seemingly obvious. Is there a builtin command to report the required ar
Hello, I am a (student) researcher working with synopsys EDA software packages for the first time. I have successfully constrained and compiled a circuit benchmark with Design Compiler (and extracted back-annotated saif), PAR with IC Compiler ( and extracted parasitics), simulated switching behavior with VCS (forward annotated saif), and am curr
Hi friends I am working on aproject name timing error detecting sequential Design for Path delay fault coverage and speedpath Identificaiton efficiency I need a help how to find setup timing error and hold timing errors? is there any command is there? I am working on synopsys primetime
synopsys design visions, report _areas is sequential cells counts = flip flop counts ?
hi, well after fixing some issues with libraries and everything else, now I encounter another error while running synopsys primepower which says : can't open init file .pt_procs.tbc before this, I was getting the following error: can't open pt_procs.tcl so I've found another one in the primetime directory and I copied it in the /auxx/tcl
please post a link to the video that you are referring to Now to your questions post-synthesis STA = synopsys primetime tool post-synthesis EC = synopsys formality or cadence conformal EC post P&R STA = synopsys primetime tool post P&R timing simulation=synopsys VCS or Cadence NCVerilog (...)
I was hoping someone can give me an idea of the list price for a few standard ASIC dev tools. Such as synopsys DC and primetime and Cadence RTL Compiler and Encounter SOC I know the actual paid price can be significantly lower and varies depending on # of seats etc. I see this has been a forum topic in the past but not for several years. I'
Milkyway is a synopsys library format that stores all of circuit files from synthesis through place and route all the way to signoff. Most synopsys tools can read and write in the Milkyway format including Design Compiler, IC Compiler, StarRCXT, Hercules, Jupiter, and primetime. Milkyway is not a free tool. You have to purchase license for (...)
Hi Dmitryl, You keep asking what exact commands/variables to use, but you have not mentioned which tool you are using inorder to tell you exactly the commands/settings necessary to enable SI analysis. Please be specific. Assuming that you are using synopsys primetime, the setting that you need to use is set si_enable_analysis true Y
I have a doubt with synopsys prime time regarding how to get timing the following step how to give the clock pins(format for declaring input and output pins) report_timing -from \ -to -delay_type max \ -path_type full_clock ?nosplit \ -max_paths 1 -nworst 1 \ -