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Dear All, When we synthesis in Design Compiler with different clk period why does the critical path changes with the change in clock period ? So does the area when viewing the report using report_qor. Please help me understand this
I am a new joinee of DESIGN AUTOMATION team.I want to learn about Synopsys Milkyway database elaborately.Plese help me.
Hello Friends I have read through synopsys DesignWare developer's guide and understood the hierarchy Synthetic operator, module,Implementation and their binding . My doubt is how registers are inferred? i mean all those coding style (Process wait, if else) infers registers but what Synthetic operator is called for and which implementation of
Hi, I am using the synosys PTPX 2010 to generate the power waveform (fsbd) file but it is in latest 4.2 version. But my viewer tool Cosmoscope (2007 version) can only support up to version4.1. Anyway I can downconvert the fsdb from version 4.2 to 4.1 or wise versa? Thanks
Cadence RC or buildgates script has synopsys-compatible mode. You can contine to write synosys scripts and run them in Cadence environment.
Hi frnds, If some one have tried using lsi_10k or other lsi libraries in synthesinzing design using synosys DC he might have faced the problem either dring the time of simulation using VCS or may be during the time of test pattern generation using TetraMax. I am facing the similar kind of problem while generating test unsing T
Is it possible to generate an spef and sbpf file of a verilog file , say addsub.v using the commands "write_parasitics -format fileformat filename" even if we dont have any parasitics to write , In synopsys primetime? plz reply
u have not mentioned the error message u have encountered.for older versions of red hat like red hat 7.2 8.0 if u use release 2003.06 it may complain of a glibc(glibc is too old in these red hat versions).for newer versions of redhat if u are running release 2003.06 u may not have nay problem.presently iam running synosys 2003.06 on rh 8.0 without
Who can give me a list of file extentions used in synopsys ASIC design flow? for example, for xilinx FPGAs I say this: *.v -> Synthesis -> *.edf then *.edf and *.edn and *.ncf and *.ucf -> ngdbuild -> *.ngd *.ngd -> map -> *.ncd *.ncd and *.pcf -> par -> *.ncd I want a same diagram for synosys ASIC design flow. Who can help?