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How to choose optimal wire width of spiral coil to attain high q factor? There are formula to calculate optimal turns n pitch. Is it by trail n error to choose wire width?
Hello, I am designing the two stage folded cascode opamp. For the single stage of folded cascode i got sufficient phase margin of 64 degree. But when i added the second stage, the phase margin increases to 150 degree. is it correct to have higher phase margin? In order to reduce the phase margin for the required level what should i do? Since i am
I was recently trying to connect my Delta VFD drive with my laptop using Vfd-Soft software (which I downloaded from Delta website) and RJ 45 to USB converter(RS232/RS485 converter). I connected the variable frequency drive to supply and connected the connecting lead to drive and pc both. I
I am making tests with a ring oscillator (RO) in ADEL cadence. But when I increase the size of the RO from 13 to 121 stages there are glitches in the output signal of the RO (image attached). How can I make the output frequency of the RO a stable signal? Because this is also generating errors for aging simulation in ADEL. 157428[/ATT
Hi, I have the following error showing up while running HFSS sim: Solving adaptive frequency ..., process hf3d exited with code -1073741819. - what's the meaning of : process hf3d exited ? - does that code have a meaning? Thanks and Regards
Looking at the *_simulation.log I found the following... # ** Fatal: (vsim-4) ****** Memory allocation failure. ***** # Attempting to allocate 131072 bytes # Please check your system for available memory and swap space. # ** Fatal: (vsim-4) ****** Memory allocation failure. ***** # Attempting to allocate 131072 bytes # Please ch
I designed a voltage doubler rectenna using qucsstudio free simulation tool. Since it is a bit more manual than ADS (with equally amazing capabilities nonetheless), there is need for extra input on the data display in terms of syntax to give you the graph you need. I have obtained the S11 and S21 plots of the rectenna but am struggling with getting
hi all right now am designing three phase protection circuit for that i planned to measure the voltage using resistor net work method, herewith i had attached my circuit and my volt measuring code, everything working good but in sometimes the R phase connected to AN0 pin shows high reading, kindly go through my code and give your valuable sugges
I have a VCVS instance in my schematic design. I can't find VCVS in layout after generate from schematic because there is no VCVS PDK in Layout. How can solve this problem? Thanks. Attached is VCVS symbol in schematic.
Hi guys, I have a schematic of OTA amplifier: 157362 I want to know the W and L that were used to design this OTA. I don't have more information other than the ones provided in this picture. since all transistors are in saturation, I thought about using the saturation current equation to find (W/L) ratio. by assuming
Hello. I am attempting to follow this circuit. I want to keep things small and cheap. How should I go about getting 5V DC for Vsupply and -1V DC (or less) for Vref? I was hoping to do this from a 9V DC source, but I am open to other ideas. I looked at voltage regulators but am not sure if I'd need a heat sink. If
Hello everyone! I want to simulate the schematic in ADS, but the problem occurs when I change a new designkit. While, I can simulate succesfully by using another designkit. Does someone know te reason? Thanks a lot157347
As a beginner to VSLI design, I am using and learning Innovus these days and have two questions. Hope someone could help me. 1) set_db. The user manual has some sample flows with codes. It usually contains 'set_db' commands to set values for some attributes (the manual calls it database object.) These object usually is the attributes belong to
Dear All, I am trying to generate test patterns for a test bench circuit "wb_conmax" by opencores. I have successfully generated the gate-level netlist. And I had successfully inserted the scan chain. However, I am unable to generate test patterns. It gives following error 157326 The script I am using to generate is as fo
Hi, For the error "incorrect ports" in Calibre LVS hierarchical run, why do some ports appear at the top level and others at the IP level ? What is the basis for them to appear at two levels like this ? Thanks, Aditya
I have a open loop TF given by 2s+100/s^2. As stated in theory, type 2 system should provide zero steady state error for velocity inputs. Could any body explain the limiting factor of this velocity. I mean, what is the maximum velocity input that this system can track?
Hello, Want to install Incisive add on to cadence DFII using Installscape on Centos 6. Do I tell Installscape where DFII installation is already and then install Incisive ? Does Incisive have to be installed before cadence DFII or can it be installed after the cadence installation ? Any special considerations for Centos ? Will (...)
Hi I am running a DRC on my design and there are some DRC markers here and there. When I run DRC again to remove these markers, I am unable to do that. It has worked fine in the previous release.
Hi all, I am an Engineering Technician, I have been soldering and de-soldering in years. I have designed and home-made toner transfer PCB as well. Now I am thinking to take course for professional PCB design for my career. I am wondering which courses I should take. Did anyone take this course, is it good for beginners? Or any recommendation?
I have a theoretical understanding of the effect of noise from different transistor and variations in different transistor. I want to know how to simulate in cadence. For for the differential amplifier - 1. Theoretically noise is done individually for each transistor and then added up. The final value will be in noise spectral density. The noi