158 Threads found on edaboard.com: Synthesis Constraints
The rule is: If your design meet constraints, it is good. Usually the need arises to improve the synthesis results, when the design fails to meet constraints. Then you will need to review may be the synthesis scripts/constraings, RTL or may be the architecture.
kr,
Avi
ASIC Design Methodologies and Tools (Digital) :: 08-21-2008 10:17 :: avimit :: Replies: 2 :: Views: 1015
Among the optimization constraints, i seen the are "max_area" constraint always setting to 0, what it really mean
During synthesis, we used the max_area 0 constraint to minimize the area of each module without violating the timing constraints.
Usually, we try to get the smallest/optimize area as possible.
Frankly, I've never
ASIC Design Methodologies and Tools (Digital) :: 08-18-2008 03:18 :: no_mad :: Replies: 2 :: Views: 1223
Hi
Let?s say there enough routing resources available, timing is fine, can you increase clock buffers in clock network? If so will there be any impact on other parameters?
How do you optimize skew/insertion delays in CTS?
What are differences in clock constraints from pre CTS (Clock Tree synthesis) to post CTS (Clock Tree (...)
ASIC Design Methodologies and Tools (Digital) :: 07-29-2008 07:34 :: snr_vlsi :: Replies: 1 :: Views: 4452
Hi
In design compiler I found after synthesisi the timing is met but the DRC s (max_transition, max_capacitance) are being violated for some of the nets. Why are there DRC violation.
Regards.
ASIC Design Methodologies and Tools (Digital) :: 06-25-2008 06:27 :: ASIC_intl :: Replies: 2 :: Views: 1732
Hi all;
I need to get the paper named:
"ILP-based scheduling with time and resource constraints in highlevel synthesis"
1- How can I get it ?
2- Please, if somone knows how to formulate the cost function of Time Cosnstrained Scheduling TCS using BLP(Binary Integer Programming) that would be more helpful
thx in advance
ASIC Design Methodologies and Tools (Digital) :: 06-21-2008 17:08 :: Samoohaa :: Replies: 3 :: Views: 1019
when including the IO PAD module ,the delay for some pad (e.g. reset_pad)is too large in critical setup timing path .Therefore,the violation is too large.can anyone help me?
Thanks!
ASIC Design Methodologies and Tools (Digital) :: 05-13-2008 02:52 :: LinXiaoling :: Replies: 6 :: Views: 1001
clock tree synthesis has to be done separately. It is done in the physical design after standard cell placement
ASIC Design Methodologies and Tools (Digital) :: 04-25-2008 05:50 :: hemanth :: Replies: 8 :: Views: 2438
DC is used for synthesis and its only for setup. so, if your DC constraints are only for setup; then you will have to define both setup and hold constraints for back-end. if input to DC is full constraints, then SDC from DC will do the job. back-end needs both setup and hold constraints, no matter whether (...)
ASIC Design Methodologies and Tools (Digital) :: 04-22-2008 16:30 :: silencer3 :: Replies: 2 :: Views: 1442
1. Questions regarding the Synopsys Setup file synthesis. Why link lib and target lib is required and order of search path .
2. clock constraints like uncertainty, clock jitter, skew and etc.
3. explain about timing path.
4. how to specify IO delays.
5. Max dealy significance.
6. Optimization techniques.
Best of luck..
Regards,
ASIC Design Methodologies and Tools (Digital) :: 04-15-2008 07:51 :: sam536 :: Replies: 2 :: Views: 3375
hi all;
in my design I generate local clock using DCM and provide a clock on output of the virtexII.
when i try to create timing constraints after synthesis using constraints editor, I don't get the clock signals there. but some other signal which are not clock they are listed as clock. I checked these signals are detected for the (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-02-2008 12:24 :: Mirzaaur :: Replies: 2 :: Views: 1162
Hi Kalyan,
Before you do Post synthesis Simulation you should decide why you need to do that. Post synthesis simulation will not give actual results as you expect on your Actual Hardware Board. So you should do Post Place-Route Simulation.
You can do that only if you know I/O constraints, Board constraints (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-10-2008 07:58 :: srinivasan_b1 :: Replies: 6 :: Views: 8099
Hi,
I think synthesis tool will ignore the delays in RTL..Depends upon ur timing constraints the synthesis tool will pick up appropriate gates from library which accounts for delays.
Thanks
sri
Elementary Electronic Questions :: 02-22-2008 13:03 :: srihari_adem :: Replies: 2 :: Views: 2212
If you have a post-synthesis SDF you can load the design netlist and SDF in Primetime, give appropriate constraints for Clock,IO and exceptions, Set operating conditions and then you can use report_timing to get the timing information
ASIC Design Methodologies and Tools (Digital) :: 02-04-2008 05:25 :: Raptor :: Replies: 2 :: Views: 928
My design was perfectly working in virtex2 without any error .when I migrate from virtex2 to virtex4 with same RTL I am getting lot of timing violation.
Violation especially OFFSET OUT AFTER constraints are not meeting.From my understanding the routing delay in virtex4 is twice that of virtex2.
I use DCFPGA for synthesis and Xilinx 9.2
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-14-2008 05:09 :: msriraman :: Replies: 0 :: Views: 787
The constraining design comes under synthesis process. The constraints mentioned by you, have their own advantages over each other.
Its all depend on you project requirment, which constraint you should put.
Go through the constraint manual of your respective tool, so that you will get better idea.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-17-2007 12:34 :: gck :: Replies: 3 :: Views: 1021
hi Shiv_emf,
Regarding the document for Clock tree synthesis constraints : layout Requirement specification, request you to visit this link. This article explains the complete hand-off which needs to be given to the layout designer who performs, the clock tree synthesis.
Praise th
ASIC Design Methodologies and Tools (Digital) :: 12-20-2007 12:33 :: vlsichipdesigner :: Replies: 10 :: Views: 5237
Normally you apply timing constraints that specify your required clock frequency, setup times, maximum skew, etc. The synthesis and place-n-route tools will try to achieve those constraints. If the tools were successful (no unhappy timing messages), and if your constraints were thorough, then your design should work (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-05-2007 03:22 :: echo47 :: Replies: 3 :: Views: 811
It is actually not related to Verilog HDL language. It is a constraint attribute for logic synthesis especially Xilinx FPGA XST synthesis.
You can search the style of entering the constraints from attached doc.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-02-2007 10:27 :: edawflee :: Replies: 2 :: Views: 866
If your synthesis tool didn't put a buffer... either you don't need it or your constraints are wrong.
Anyway, you can write a simple script that inserts a buffer in particular net if you want to.
ASIC Design Methodologies and Tools (Digital) :: 09-25-2007 10:43 :: Thinkie :: Replies: 11 :: Views: 1978
Suppose I have a number processors connected to a shared bus interconnect, as well as a number of slave devices. In a real design, how is something like that clocked/timed/constrained. I can't imagine that they all use the same clock domain. Can anyone provide some insight, what would an actual synthesis script look like?
ASIC Design Methodologies and Tools (Digital) :: 08-29-2007 04:01 :: ed271828 :: Replies: 0 :: Views: 952