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19 Threads found on Synthesis Design Issues
Is there any software or tool with which i can separate out synthesizable and non sythesizable code from a given verilog code? I'm pretty sure that there's no such thing. The ability to tell which code can or cannot be synthesized to real logic is an integral ability of any synthesis tool - once the tool sees something "illegal" th
Hi All, Wanted to know what are the common design related issues faced during doing synthesis. Please list it down for clarification. Thanks Limitless_21
Hello Friends, At this time I have a question for skill sets. I have worked on DC synthesis - Full chip upto certain extent. have idea about design contraints, scan insertion, timings; along with that I have resolved some of the real issues which were present in DC netlist. But my question is - How do I say that I know Full chip (...)
I am working on a design which has hierarchy structure like this: .top_level_hier ......| ......- wrapper_hier ............| ............- lower_hier ..................| ..................- even_lower_hier I am running DC-topo synthesis. Due to some issues caused by voltage area coverage in later stages in ICC, I need to (...)
Greetings colleagues, I am currently working on the Synopsys Low Power Flow Workshop (Lab 3 synthesis). The library files used in this design are : 1) saed90nm_hvt_rdsr.db 2) saed90nm_lvt_rdsr.db 3) saed90nm_max_hth_hvt_rdsr.db 4) saed90nm_max_hth_lvt_rdsr.db I have specified the operating condition for the design as WORST in the (...)
If we know that about CDC crossings in design . Do you see that we can take advantage of such reports during the synthesis (may be on the crossing synthesis tool is trying to put more effort to meet the timing etc)?:?: regards sakshi
hello , i have generated a blockram using coregen and it has a we(write enable) i dont need that so ,i need to keep this always enabled..... so how can this be done? in the toplevel module calling this block with 1'b1 is ok...? ie bram u1(.we(1'b1),.dina(dina......) is that ok? will this code connect we to vcc?
Hi, My design is working perfectly good after the post-synthesis (using DC) at clock rate of 5 ns. In place and route(using encounter), I got 50 setup violating path. I tried to simulate the netlist and it worked but with a clock of 40 ns (might be not the corner but it didn't work with 5 ns or even 20 ns). My question:
look at the synthesis report. You most likely have all of your logic removed in synthesis for some reason. most likely, the tools will explain that l1hits is never referenced. with no outputs, the inputs are considered to be useless. now the design itself will likely have sim issues as well as implementation (...)
Please do provide some solutions for these queries as i need to know the solutions Somebody correct me if I am wrong... 1. What kind of issues or a report does a Backend Physical design guy give to the synthesis guy ones he has received the netlist. And what checklist should be done by th PD guy before starting off the flow.
Hi All, Can someone point to the kind of issues that the physical design team reports to the synthesis team, after the netlist is released to them for entire Physical Flow. Thanks, Nik
SV will win as it's not linked to just one Vendor and also addresses synthesis issues as well.
I dont get the question. usually you just develope your general design with VHDL or verilog and then you can use synthesis and simulation tools to check wether a specific device is suitable or not(regarding resource usage, timing specs and financial issues...). buying the FPGA is the last step.
The constraining design comes under synthesis process. The constraints mentioned by you, have their own advantages over each other. Its all depend on you project requirment, which constraint you should put. Go through the constraint manual of your respective tool, so that you will get better idea.
basic RC do synthesis is interms of GLOBALLY. Dc do optimization in the timing path. but RC first take timing (cpt) do optimization . then none critical path RC do area,power optimization. so it can achieve tradeoff between area,time ,speed
design compiler integreted with DFT complier can synthesis rtl code to a scan chain ready netlist, but I dont know how to generate those test control signals and components. For example, How to connect port enable the "shift" cycle named scan_en to all dffs? When memories are used in design, a bypass mux controlled by signal scan_mode (...)
Hi Friends, i am working on SoC Encounter which is Place & Route tool in which u can do RTL synthesis also. so i would like to know some issues regarding the RTL synthesis step, Basically i will get Gate level Netlist from the PKS tool & same netlist i wiil use input to the SoC Encounter. So i want to know what r effects of 1) (...)
hi what's this feature in synthesis tools? gracias
Gentlemen, I design highspeed / low noise digital circuitry in bipolar. I would like to use VERILOG to describe e.g. counter in on RTL level and then synthesize it into differential gates. The issues I have are: need of several voltage levels to avoid device saturation, need of emmiter followers, AND/NAND/OR/NOR/ could be just a one cell with tw