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106 Threads found on edaboard.com: Synthesis Encounter
Hi friends, I am using encounter 13.26 . After synthesis, I import the netlist/lef/lib/io/etc to encounter. But in the floorplan view, I can not see any module. Since I am trying to use Top-bottom hierarchical flow, and there are several modules in the design. I want to make one of them as a partition. The question is how can I view (...)
Hi, As the title of this topic indicates, I want to synthesise and P&R a design without buffers in order to observe the behaviour of long interconnects to the delay. Therefore, I want to know if there is any way to disable buffer insertion to my design, both at the stage of synthesis (Design Compiler - Synopsys) and the stage of place and route
Hi all, I am working on a DFT . its an academic project where iam using cadence tools - genus synthesis solution (formerly RTL compiler) for DFT and encounter test(ET) for ATPG. now the question is, after performing DFT synthesis, i was supposed to write ET scripts which were used by ET for generating testpatterns with the command : (...)
We really feel sorry for you, but what else can we do! Hi, When i am doing clock tree synthesis then encounter is automatically terminated. By showing this error. **ERROR: (ENCCK-1044): Due to earlier errors, failed to generate consistent RouteType FE_CTS_DEFAULT. Your post
Hi While doing HFNS i got the high fanout nets using the dbGet command. but when i give buffertree synthesis command it says, two nets have no driver so It shows an error message and it aborts the buffer tree synthesis operation. The net it is telling "no driver" is actually a pin of macro. Do i need to give any special command?
Hello, I'm designing a simple circuit using Multi Supply Voltage. I'm using synopsys Dc Compiler for synthesys, therefore I must use UPF. For the physical implementation I will use Cadence encounter which doesn't support UPF, but requires a CPF. Since my design is simple (I have only one power mode) the translation from UPF to CPF is sim
Hi I want to know best synthesis tool for asic design. From web i have listed some like 1. Design Compiler by Synopsys 2. encounter RTL Compiler by Cadence Design Systems 3. HDL Designer by Mentor Graphics 4. TalusDesign by Magma Design Automation I know it might be difficult to say best because it might depends on what to implemen
Hi I want to know best synthesis tool for asic design. From web i have listed some like 1. Design Compiler by Synopsys 2. encounter RTL Compiler by Cadence Design Systems 3. HDL Designer by Mentor Graphics 4. TalusDesign by Magma Design Automation I know it might be difficult to say best because it might depends on what to implemen
Dear All, I have a .v file and i have done scan synthesis using RTL Compiler. Now how to approach for doing ATPG using the encounter TEST(ET)? Do I need to export the scan.def file to ET for doing atpg/ fault analysis? I don't know the exact command to do this export thing. Kindly Help ASAP.
Hi, I am new to APR so please excuse me if my questions seem lame. Should the netlist output from synthesis have VDD/VSS ? Also, Do I have to add Power rings in encounter to be able to place std cells ? As I do place but nothing appears in the layout . Thanks
The post synthesis netlist should ideally not give you any problems. Can you check whether the clocks and resets are correct?
STA can be run on 2 occasions : pre-layout & post-layout. Pre-layout STA requires the post synthesis netlist & constraints. Post-layout requires the P&R netlist, the constraints & the SPEF file generated from a tool like STAR RC. If you have a "gate level netlist form synthesis", then you must be doing pre-layout STA. You don't need anything else
Hi, I am getting an error while doing clock tree synthesis in encounter 10.1. It showing that **ERROR: (ENCCK-158): Cannot find output terms for clock clk_in/ANAIO. Here pad inastant name is "clk_in" and pin name is "ANAIO". CLock tree specifile started like AutoCTSRootPin clk_in/ANAIO NoGating rising #(for auto CTS on a net) Bu
Hi, I am getting an error while doing clock tree synthesis in encounter 10.1. It showing that **ERROR: (ENCCK-158): Cannot find output terms for clock clk_in/ANAIO. Here pad inastant name is "clk_in" and pin name is "ANAIO". CLock tree specifile started like AutoCTSRootPin clock clk_in/ANAIO
In RTL, clock buffers and MUXes are used to create a delay chain/tapped delay line. These are preserved in synthesis and hence they appear in the netlist. If this netlist is used, during Clock Tree synthesis (CTS) stage, the tool (SoC encounter) hangs and does not move forward saying that the clocks are already built and cannot be removed. (...)
hi friends, I have started working on cadence soc encounter. when I am writing code on verilog , no errors will be found when I am doing my synthesis. But when Iam writing a code in VHDL, lot of errors are found when iam doing my RTL synthesis. Is it cadence soc encounter will only work for VERILOG, or VHDL or both. Ramya
synthesis is done using RTL compiler from cadence, Design Compiler (DC) from synopsys. Routing is done by PNR tools Cadence encounter uses Nanorouter for routing. ICC also have it own routing engine. There are very good documents related to ASIC design are available at below link.
when i am using dc_compiler for synthesis i have a problem in passing dc_compiler files (netlist ,sdf) to encounter as i have to modify my netlist and make pin assignment in in , my Question is their a solution for this problem , as in large chip with huge IO how i can make the
There are many aspects to cause the size different, both tools are running with different optimization method, this is normal to have size different but not more than 20% different btw both. I only can guess the constraints in both could be different, e.g in synthesis you have use WLM, (top, enclosure, segmented) but i synthesis the RC are calcul
I'm running a synthesis using RTL Compiler and I need a captbl file for physical synthesis for the interconnect RC extraction models. I can find .ict files but I don't have a .captbl file. How can I create one of these or which software do I use?