170 Threads found on edaboard.com: Synthesis Power
According to this post the question is for the filter written in vhdl code the multipliers that i have used in the code is 164 multipliers per the fpga there are total 192 multipliers But the synthesis report it shows 148 multipliers and the filter coefficients are symmmetrical.I doubt whether during the optimization of the code the it has redu
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-13-2013 15:37 :: kannan2590 :: Replies: 18 :: Views: 960
Hi,
I use Design the setup part(file/setup), there is three type (fast,typical and slow with 1.32 ,1.2 and 1.08 supply voltage ) in 130nm cmos technology.
when I synthesis code, the result received for power, in slow type is bigger as typical type. while the supply voltage in slow is smaller than typical.
ASIC Design Methodologies and Tools (Digital) :: 02-13-2013 08:22 :: electronical :: Replies: 0 :: Views: 581
Take a step back and ask if there's any good analog
synthesis, at all.
Digital, you have about 3-4 care-abouts - area, power,
timing closure, functionality.
Analog, you typically have dozens of parametrics per
block as well as noise, matching, stability, input / output
ranges and impedances. Making specification alone, a
big hassle and
Elementary Electronic Questions :: 02-06-2013 17:54 :: dick_freebird :: Replies: 2 :: Views: 605
I'm an analog guy trying to make sense of digital tools
a) once you APR a block through ICC, do you do a LVS on APR output. If so, how? for synthesis I know you do conformal or some equivalence checking, what do you do after Layout. do you compare the CEL format with Gate level netlist or RTL
b) Typ RTL has no power pins and I think the .syn wi
ASIC Design Methodologies and Tools (Digital) :: 01-24-2013 01:42 :: love_analog :: Replies: 0 :: Views: 466
You must do a synthesis to be able to have an accurate estimate.
This URL may help you:
ASIC Design Methodologies and Tools (Digital) :: 01-05-2013 02:06 :: alexhugo :: Replies: 2 :: Views: 708
Hi to all
i have power report after synthesis using synopsys design compiler and there is many power type
Cell internal power =
Net switching power =
Total dynamic power =
cell leakage power =
so i need what power my design consume (...)
ASIC Design Methodologies and Tools (Digital) :: 12-22-2012 18:35 :: omar-malek :: Replies: 1 :: Views: 826
What exactly are the challenges that one faces when you go from say 65nm to 32nm and also in terns frequency where we use gigahertz scles
During synthesis or during place and optimization
ASIC Design Methodologies and Tools (Digital) :: 11-30-2012 07:42 :: englishdogg :: Replies: 2 :: Views: 630
the question is way to high level to have a precise answer - first which power leakage or dynamic
some optimizations / tricks mentioned below
- Clock Gating
- Annotating activity during synthesis
- MultiVt synthesis
- use CPF / UPF to achieve more savings depending on design architecture and application for eg power Shut (...)
ASIC Design Methodologies and Tools (Digital) :: 11-30-2012 07:16 :: englishdogg :: Replies: 1 :: Views: 600
Hi Guys.
When I am doing power network synthesis and power network analysis in ICC, I met some curious things.
I did two experiments on power network synthesis. EXP1: with the standard cells placed. EXP2: with the standard cells unplaced.
Then I used the same PNS script do (...)
ASIC Design Methodologies and Tools (Digital) :: 03-17-2011 06:21 :: owen_li :: Replies: 3 :: Views: 2345
Greetings colleagues,
I am currently working on the Synopsys Low power Flow Workshop (Lab 3 synthesis). The library files used in this design are :
1) saed90nm_hvt_rdsr.db
2) saed90nm_lvt_rdsr.db
3) saed90nm_max_hth_hvt_rdsr.db
4) saed90nm_max_hth_lvt_rdsr.db
I have specified the operating condition for the design as WORST in the library
ASIC Design Methodologies and Tools (Digital) :: 10-04-2012 11:43 :: kushan_s :: Replies: 0 :: Views: 1210
Hi,
I have a post-synthesis gate-level net-list derived from Synopsys DC. I have used power gating specified using UPF.
Now I want to make power-Aware Gate-Level Simulation in Modelsim, but it does not work properly.
Can anyone help?
Is there any tutorial?
ASIC Design Methodologies and Tools (Digital) :: 09-09-2012 09:17 :: hayoula :: Replies: 0 :: Views: 897
Dear Friends,
I have 5+ yrs of experience in synthesis, Physical synthesis, Low power, DFT, Placement , Pre-CTS Optimization, Formal verification, Flow / Methodology setup, ECO, Timing Closure / analysis, QoR and TCL Coding.
I am looking for a change now - either in design companies or EDA product companies.
I am currently based in (...)
EDA Jobs :: 08-24-2012 13:06 :: englishdogg :: Replies: 0 :: Views: 833
1. Micro Architectural Review(FLOW Diagram Level) from all aspects like Timing Area power.
2. Once above is approved RTL coding starts
3. All Frontend Checks
4. Constraints
5. synthesis
6. Deliverable to Physical Design
ASIC Design Methodologies and Tools (Digital) :: 08-20-2012 07:35 :: dftrtl :: Replies: 2 :: Views: 551
I'm using Synopsis DC for synthesis.. I get a warning in the multi voltage check report saying that "the isolation cell A connecting pins C (related supply net X) and D (related supply net Y) maybe redundant. Supply net Y is always on or more or less equal to supply net X".. Wat does it mean exactly?? And how to clear this warning??
[COLOR="silv
ASIC Design Methodologies and Tools (Digital) :: 08-17-2012 04:35 :: Sumitha Sudhakaran :: Replies: 3 :: Views: 1512
hai friend
you can refer this document , i hope this might help you
when you synthesis your design you will get the total power required your total no of cells
thank u
ASIC Design Methodologies and Tools (Digital) :: 07-30-2012 03:40 :: vimalraj205 :: Replies: 2 :: Views: 1434
A lots of shift register is used in delay line in my design, which consumes significant power. Is there a method of telling the rtlcompiler to synthesis the code to TSPC register rather than the master-slave register?
Thanks in advance.
ASIC Design Methodologies and Tools (Digital) :: 07-11-2012 19:59 :: razorj :: Replies: 0 :: Views: 582
Hello all:
I am estimating power of a post-synthesis using a VCD based flow using Primrtime-PX. I am using following command for reading the vcd file:
read_vcd -rtl -strip_path tb_registerfile/UUT reg.vcd
and it is printing out the following messages to console
Information: Reading file reg.vcd to annotate toggle rates on the design...
ASIC Design Methodologies and Tools (Digital) :: 07-02-2012 18:39 :: achundur :: Replies: 6 :: Views: 1356
Hi,
I want to synthesis my VHDL code in design compiler.i want to use 90nm libaray.i have wriiten UPF for power gating implementation..
Can anyone tell me which library i should use for this purpose.i have SAEDPDK_EDK folder which contains many library .
ASIC Design Methodologies and Tools (Digital) :: 07-02-2012 14:10 :: anuradha.verma :: Replies: 0 :: Views: 909
powerCompiler (or DesignCompiler, as PC does not have own interface) may insert isolators, level shifters, always-on buffers, retention registers during synthesis.
power gating cells are inserted after synthesis by PnR tool (like Synopsys IC Compiler).
ASIC Design Methodologies and Tools (Digital) :: 06-27-2012 13:14 :: oratie :: Replies: 4 :: Views: 2587
If your library has power switches and isolation cells , you can follow "low power synthesis Flow" of Synopsys Design Compiler to power gate each section of your design.
You must refer to "Synopsys? Low-power Flow User Guide Document.
This web page could help you a lot too :
ASIC Design Methodologies and Tools (Digital) :: 05-23-2012 07:45 :: Oveis.Gharan :: Replies: 12 :: Views: 2251